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DDR Self Refresh Mode

ajit basarur
Intellectual 410 points

Hi All,

I am working on a custom OMAP3730 based board with custom WinCE BSP on the same. We have implemented power management for the same.

Now in the process of implementing DDR self refresh mode during suspend state.  To test the DDR self refresh mode, I am currently testing it at the x-loader level since it executes from Internal RAM (IRAM) context.

I have x-loader code which initializes DDR before passing the control to DDR. I am halting the x-loader booting immediately after DDR initialization and trying to observe current consumption using power supply bench with current resolution set for mA.

My x-loader code implements the following

1.) Initialize ARM,  DSP & Core clocks

2.) Initialize PINMUX settings

3.) Initialize Flash Interface 

4.) Initialize DDR

5.) Enter Wait for Interrupt Mode (WFI)

Now I have implemented the following step between step 4 and step 5.

4.1.) Put DDR in self refresh mode by updating the register ( SDRC_MANUAL_0 & SDRC_MANUAL_1 with 0x5, enter self refresh command)

I do not observe any current difference when I put the same in DDR self refresh mode.

I just want to check if anybody has tried putting DDR in self refresh mode and observed the current difference?

Any suggestions will be really appreciated.

 

Thanks,

Ajit

  • 0
    TI__Guru* 86820 points

    Ajit, i would recommend trying to use the SRFRONIDLEREQ bit, which manages the self refresh better.  The SDRC_MANUAL register you are using just sends a self refresh command, but doesn't turn off clocks or do anything else associated with self-refresh (CKE changing state, for example), so i don't think the memory if truly getting into self-refresh. 

    I would recommend checking out:  http://processors.wiki.ti.com/index.php/Power_Management_CCS_project_for_OMAP35x_and_AM-DM37x

    This wiki has a CCS project which that can be run on the EVM which demonstrates going into and out of OFF mode.  Although you are using WInCE, this should give you a good example to start with.

    Regards,

    James 

  • 0 in reply to JJD
    Intellectual 410 points

    Hi James,

    Thanks for the timely response. Yes I have used the SRFRONIDLEREQ bit provided by SDRC itself. But I do not observe any power difference in the system. I had a look into the code recommended by you and it does the same thing. My idea is to just measure the power difference when DDR is in self-refresh mode and in normal mode. Your any other suggestions or links to power measurement reports will be greatly valued.

    Thank again for the quick and useful response.

    Regards,

    ~Ajit

  • 0 in reply to ajit basarur
    TI__Guru* 86820 points

    Ajit, I'm not sure how you are measuring power, or where in the system you are measuring.  If possible, you can supply the 1.8V for the memory separately to truly get an indication of how much power it is drawing in each mode.  If you try to measure at the system level (eg, from the main 5V power supply to the PMIC), you may not be able to see a difference.

    I think an easy way to check to see if you are going into self refresh is to check the ddr_cke signal.  This should be low during self refresh, and high during normal operation.

    Regards,

    James 

  • 0 in reply to JJD
    Intellectual 410 points

    Hi James,

    Thanks for the suggestions. I do not have any means to measure current over 1.8V supply provided to DDR. Also there is no way in our system or even in OMAP OSK to probe and validate the CKE signal. So I am also not sure about if DDR is entering self refresh mode at all.

    Regards,

    ~Ajit