AM623: eMMC configuration and initialization sequence

Hello,

Tony Tang said:

#1.  mmc-ddr-1_8v; is removed until SDK11.01, is it for DDR50 mode?

Yes, as per the following commit.

git.ti.com/.../

Tony Tang said:

#2.  The clock items are removed after SDK10.1, what is the impacts as it exists in SDK9.2.

Please check if the commit message is sufficient

git.ti.com/.../

Tony Tang said:

#3.    ti,otap-del-sel-ddr52 = <0x5>; is removed after SDK10.0.  will DDR52 mode be configured during initialization if it exist?

No, if there is a higher speed mode available.

Tony Tang said:

#4. When initialize eMMC, will the driver configure it from low to higher speed one by one according to otap/itap paramter items? or get the highest capability from eMMC, configure to the highest speed in one step?

It configures in the highest mode possible by checking the card capabilities and the DTS properties.

Tony Tang said:

If customer keeps on old SDK8.3 and SDK9.2, should they change the dts to that of SDK12 to remove mmc-ddr-1_8v, clock item, and  ti,otap-del-sel-ddr52 = <0x5>; will that work?

I am not sure about the clock changes but removing the DDR50 related properties should not cause issues.

Prashant Shivhare said:

It configures in the highest mode possible by checking the card capabilities and the DTS properties.

If the eMMC supports HS200, no matter mmc-ddr-1_8v and ti,otap-del-sel-ddr52 = <0x5>;exist or not, it won't matter. and won't have 50MHz eMMC_CLK stage before entering HS200 mode?

BTW, what is the mode configured by ROM code stage? is it 25MHz legacy SDR mode?

Tony Tang said:

and won't have 50MHz eMMC_CLK stage before entering HS200 mode?

The eMMC HS200 initialization sequence doesn't involve the DDR50 speed mode.

Tony Tang said:

BTW, what is the mode configured by ROM code stage? is it 25MHz legacy SDR mode?

I will have to check.

Prashant Shivhare said:

The eMMC HS200 initialization sequence doesn't involve the DDR50 speed mode.

But customer captured all frequency during booting up with SDK9.2.1.09: 400K---25M---400K---25M---50M---400K---50M---200M

below is the 50MHz DDR stage.

uboot k3-am62-main.dtsi

	sdhci0: mmc@fa10000 {
		compatible = "ti,am62-sdhci";
		reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>;
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 57 5>, <&k3_clks 57 6>;
		clock-names = "clk_ahb", "clk_xin";
		assigned-clocks = <&k3_clks 57 6>;
		assigned-clock-parents = <&k3_clks 57 8>;
		bus-width = <8>;
		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		ti,clkbuf-sel = <0x7>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-mmc-hs = <0x0>;
		ti,otap-del-sel-ddr52 = <0x5>;
		ti,otap-del-sel-hs200 = <0x5>;
		ti,itap-del-sel-legacy = <0xa>;
		ti,itap-del-sel-mmc-hs = <0x1>;
		status = "disabled";
	};

Seems it is negotiating from low to high clock frequency across dts parameter. And asked AI got same conclusion.

The HS400 mode does involve switching to DDR but not HS200.

git.ti.com/.../mmc.c