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TMS320DM8168: Queries regarding Video Input Processing and Codec Capabilities of TMS320DM8168

Nilesh mahajan
Prodigy 26 points

Part Number: TMS320DM8168

Hi TI team ,

                I am working on TMS320DM8168 processor and would like to clarify a few points regarding its specifications. 

1) Support for Interlaced and Progressive Video Input?
Does the HDVPSS (High-Definition Video Processing Subsystem) natively support both interlaced and progressive video capture? 
 
2) H.264 Decoding of Interlaced Ethernet Streams
We are receiving a compressed, interlaced PAL H.264 video stream via 1GbE Ethernet. Can the HDVICP2 (IVA-HD) subsystem natively decode this interlaced H.264 stream?
 
3) Post-Decoding Output Format (YCbCr)
Following the H.264 decoding process, can the DM8168 provide the decoded output in YCbCr 4:2:2 (YUYV) format? 
 
4) Simultaneous Interlaced Input/Output (I/O) Operations
Does the architecture support concurrent interlaced video capture and interlaced video display?