Part Number: TDA4VH-Q1
Hi Experts,
We are currently using J784S4 evm with SDK 11.2
We are using FreeRTOS with 5 tasks on c7x cores. And our app is time critical and is based on interrupt.
We noticed c7x interrupt latency around 3 to 5 us. This latency is measured between the moment the trigger occurs and the context switch to the task waiting for the interrupt.
every c7x interrupts are concerned (GPIO, DMA, etc).
MSMC is config as 8MB SRAM, L1D is 16KB SRAM + 32KB cache (for our application needs).
85% of the latency comes from Hwi_dispatchAlways function. Which is an ASM function that copy c7x register into the stack.
It seems that the latency comes from the time to copy c7x reg to the stack. the performance is impacted by the cache :
- case 1 we interrupt c7x once : latency is ~3 to 5us
- case 2 we interrupt c7x several times : average latency is ~750 ns (except the first one 5us latency)
- case 3 we interrupt c7x several times with cache invalidate of the stack + the ASM code : latency is ~3 to 5 us every times
seen from lauterbach probe (self trigger interrupt unit test) :
The latency depends of the memory used for the stack :
- stack in DDR : latency = 4 us
- stack in MSMC : latency = 3,4 us
- stack in EL2: latency = 2,1 us
Our stack is too big and can't be moved to L1D or L2.
We have done a workaround to save c7x register into L1D instead of the stack (we have implemented an "ISR stack"). We achieved a latency of 700 ns for every interrupts. The workaround handle nested interrupts. But it is unstable with several freeRTOS tasks, We think it comes from saving the context from different tasks.
Could you help us to reduce this latency ? By providing your solution or helping us to improve our workaround.
Regards,
Charles
