Part Number: AM62A7-Q1
Hi, TI expert
Environment:
SOC: AM62A7-Q1
SDK: mcu_plus_sdk_am62ax_10_01_00_33
DDR: Micron 2GB 200b-z42m-automotive-lpddr4x-lpddr4.pdf
DDR cfg: 1865MHz ddr_cfg(am62a7_2GB_1865_MT).zip
Question:
After enabling inline DDR ECC, we conducted stress test and encountered an ECC error interrupt,
When inline DDR ECC is disabled, there are no abnormalities when using memtester. May I ask if the margin is insufficient, or if the timings are too aggressive?
DDR Enable Procedure:
1. Set DDR ECC config in SBL1
2. Apply the patch
4. Reading register 0x0f300120 shows that ECC is enabled.
Question:
After enabling inline DDR ECC, we conducted stress test and encountered an ECC error interrupt,
When inline DDR ECC is disabled, there are no abnormalities when using memtester. May I ask if the margin is insufficient, or if the timings are too aggressive?
DDR Enable Procedure:
1. Set DDR ECC config in SBL1
2. Apply the patch
/cfs-file/__key/communityserver-discussions-components-files/791/ddr_5F00_11_5F00_1.patch
3. Update dtb in u-boot-spl & u-boot & kernel4. Reading register 0x0f300120 shows that ECC is enabled.
Best regards!
XUE Fadong
