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AM5749: Package delay time for AM5749 DDR interface

Stephen Williams
Prodigy 20 points

Part Number: AM5749

I'm looking at designing a custom board around the AM5749 and require package delay information for pads associated with the EMIF1 interface to ensure DDR3 timing constraints are met.

Having looked at the data manual this information wasn't obviously available, is there a table of delays (e.g. in picoseconds) associated with each of the EMIF1 pads?

Thanks for your help,
Stephen

  • 0
    TI__Mastermind 43500 points

    Hi,

    My understanding is that we do not provide package delays for AM57x devices.

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Prodigy 20 points

    Does this mean that the package delays across the DDR pads are sufficiently small there is no need to account for them in the PCB layout?

    Sorry, need to be clear about this before committing the cost / effort / elapsed time of board spin.

    Kind regards,
    Stephen

  • 0 in reply to Stephen Williams
    TI__Mastermind 43500 points

    Hi,

    Stephen Williams said:

    Does this mean that the package delays across the DDR pads are sufficiently small there is no need to account for them in the PCB layout?

    Sorry, need to be clear about this before committing the cost / effort / elapsed time of board spin.

    I'll check again, but as I understand, we did not provide package delays for AM57x devices. The databook (section 7.2) should provide guidelines including a routing specification documenting max trace lengths / skews. 

    Regards,
    Kevin

  • +1 in reply to Kevin S
    TI__Guru 56967 points

    Right, we don't provide package delay info since a) the routes are tiny and well matched, and b) the layout guidelines appnote builds in sufficient margin to account for any skews that are outside of the PCB contribution.

    Regards,

    Kyle