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6748 & CSL Question

Alex T Wilson
Prodigy 325 points

Question from a customer:

This question "pertains to the CSL (Chip Support Library) for the C6748 processor.

You publish a document specifically describing the cache controller for the C674x family of processors (sprug82a.pdf).

In here you show some sample code to program the Cache using the CSL and you reference some stuff (see example(s) below:

for (i=0; i<(DATASIZE/BUFSIZE)-2; i+=2)

{

/* ----------------------------------------------------- */

/* InBuffA -> OutBuffA Processing */

/* ----------------------------------------------------- */

CACHE_InvL2(InBuffB, BUFSIZE, CACHE_WAIT);

<DMA_transfer(peripheral, InBuffB, BUFSIZE)>

CACHE_wbL2(OutBuffB, BUFSIZE, CACHE_WAIT);

<DMA_transfer(OutBuffB, peripheral, BUFSIZE)>

process(InBuffA, OutBuffA, BUFSIZE);

/* ----------------------------------------------------- */

/* InBuffB -> OutBuffB Processing */

/* ----------------------------------------------------- */

CACHE_InvL2(InBuffA, BUFSIZE, CACHE_WAIT);

<DMA_transfer(peripheral, InBuffA, BUFSIZE)>

CACHE_wbL2(OutBuffA, BUFSIZE, CACHE_WAIT);

<DMA_transfer(OutBuffA, peripheral, BUFSIZE)>

process(InBuffB, OutBuffB, BUFSIZE);

}

 

And:

#pragma DATA_ALIGN(InBuffA, CACHE_L2_LINESIZE)

#pragma DATA_ALIGN(InBuffB, CACHE_L2_LINESIZE)

#pragma DATA_ALIGN(OutBuffA,CACHE_L2_LINESIZE)

#pragma DATA_ALIGN(OutBuffB,CACHE_L2_LINESIZE)

unsigned char InBuffA [N*CACHE_L2_LINESIZE];

unsigned char OutBuffA[N*CACHE_L2_LINESIZE];

unsigned char InBuffB [N*CACHE_L2_LINESIZE];

unsigned char OutBuffB[N*CACHE_L2_LINESIZE];

These functions and defines don’t seem to exist anywhere. If I look in the older chips (like the C6713) these are defined in the CSL for that chip (in fact, they are defined for the C6457 in the CSL for it). According to the links I’ve found from TI the CSL for the C6748 is part of the BIOSPSP (http://processors.wiki.ti.com/index.php/Chip_support_library#Chip_Support_Library_for_C6747_and_C6748).

These defines and functions are not part of this package.  In fact, it looks like this package is a collection of TI’s drivers for various on chip peripherals, not a true CSL which might be used to write your own driver.

So my question is, since these examples are in the Cache C674x document I assume the equivalent to the old CSL is available somewhere. Where can I get it? I’ve looked around and I cannot find it. I did find it for the C6457, which we also use, but I can’t believe that TI would provide a CSL set of subroutines to manage on chip peripherals for one family, but not for another.

Can you please help me locate it?

  • 0
    TI__Mastermind 18320 points

    Alex,

    This post was moved to the BIOS forum, but I believe that each chip's CSL is actually authored by the device team, so I have moved this thread over to the C674x forum in hopes that it will get a faster response there.

    Dave

  • 0
    TI__Expert 8890 points

    Alex,

    I'm not sure where the CACHE APIs exist (or previously existed), but you have a few different options for cache support on C6748.  First, DSP/BIOS provides cache APIs.  In DSP/BIOS 5.x, you can use the BCACHE APIs, which are documented in the user guide.  In SYS/BIOS 6.x, BCACHE was replaced by Cache, which provides similar APIs.

    If you don't want to use BIOS, I recommend taking a look at StarterWare for C6748.  StarterWare is an OS-independent software package that provides support for cache management, among other things.  The cache APIs in StarterWare are part of the "system_config" library in that package, and they are very similar to the DSP/BIOS cache APIs.  You can find a link to download StarterWare for C6748 (and more information about StarterWare in general) at the following URL:

    Once you've installed StarterWare, you can find the source code for the C674x cache APIs in the file system_config/c674x/cache.c relative to your StarterWare installation.

  • 0 in reply to Joe Coombs
    TI__Prodigy 325 points

    Joe,

    Thanks for the answer, here is the reply from the customer:

    "I’ll take a look at this stuff and get back to you.

    They still haven’t really answered the question though: Where’s the CSL for the C67x family that provides a similar API to the old CSL? The confusing part comes from a couple of places:

    1. The CSL API is available for the C64x+ family of chips. In fact, you can get the source code for it, and in that source I can see things that lead me to believe that this code was also planned to be available for other chips, like the C67x family (based on the registers being included in the build from ifdef’s).
    2. The C67x documentation actually provides code examples using the old CSL API’s in examples

    The psp stuff that TI says is the CSL for the C6748 is not functionally equivalent to the older CSL stuff. We have large code bases using the on-chip peripherals (cache, McBSP, SIO, EDMA, etc) through the CSL and apparently it is now all throw away. There is no real porting option that I see, other than perhaps adapting the CSL for the C64x+ family (since I have the source) to the C67x chips.

    Could you press them for an answer in regards to the CSL API question for the C674x family: Is TI really, as a company, going forward with a CSL API for the C64x+ family of chips that will in no way be portable to other DSP families, despite the fact that the on-chip peripheral devices and registers that control them are almost identical between these two families?"