Part Number: AM3352
Hi
Recently, when using the TI AM335X chip to control DDR3, we found that the time between the rising edge of the RESET signal and the rising edge of the CKE signal is only 112µs, which does not conform to the DDR3 standard.
<image001.jpg>
<image002.png> I conducted the following experiments after reading the code.
Experiment 1: Execute the following commands sequentially: (1) SDRAM_REF_CTRL=0x80003100; (2) SDRAM_CONFIG = 0x61C04AB2; (3) SDRAM_REF_CTRL=0x00003100; (4) Delay for 1ms. We found that the reset signal and CKE have a 112us interaction time, which does not conform to the standard.
Experiment 2: Execute the following commands sequentially: (1) SDRAM_REF_CTRL=0x80003100; (2) SDRAM_REF_CTRL=0x00003100; (3) SDRAM_CONFIG = 0x61C04AB2; (4) Delay for 1ms. We found that the reset signal and CKE have a 600us interaction time, which conforms to the standard. Our DDR3 clock speed is 303MHz. I don't understand why the SDRAM_REF_CTRL=0x00003100 operation must be placed before SDRAM_CONFIG = 0x61C04AB2 to ensure the expected time slot between the DDR3 reset initialization eset signal and CKE.
You can easily find this code by downloading the latest U-Boot code; the file path is
<image003.png>
You can modify the config_sdram function.
The image below is from section 7.3.3.6.2 DDR3 Initialization of the AM3352 manual. The manual explicitly states that this time should exceed 500µs; and theoretically, the default u-boot code should achieve a time interval exceeding 500µs between the reset and CBE rising edges.
However, in reality, the u-boot software execution time is only 112µs. The execution register order needs to be adjusted to achieve a time interval exceeding 500µs.
Thanks
Zekun
