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C6747 reset input pin transition time

Hirofumi Fujita
Intellectual 1780 points

Other Parts Discussed in Thread: OMAPL138

Hi,

 According to "5.2 Recommended Operating Conditions" of the "www.ti.com/lit/ds/sprs377d/sprs377d.pdf" ,  it is recommended to realize less than "0.25P or 10 " ns transition time for general input pin.

 Is it also recommended to Reset pin (G3)  ?

best regards,

Hirofumi Fujita

  • 0
    TI__Intellectual 1780 points

    Hi,

     I thought that, this reset timing requirement was too much strict, and even much slower rise time should work for usual reset behavior.

     But as my second thought,  it is needed to define the minimum timing requirement of " tsu(BPV-RSTH), Setup time, boot pins valid before RESET/TRST high" and  "th(RSTH-BPV), Hold time, boot pins valid after RESET/TRST high". So when the user takes much longer time for "tsu(BPV-RSTH)" and "th(RSTH-BPV)",[ 0.25P or 10]nsec rise time is not mandatory for G3 reset pin.


     Is that understanding correct?

    best regards,

    Hirofumi Fujita

  • 0 in reply to Hirofumi Fujita
    TI__Guru* 85095 points

    Fujita-san

    You are correct, the 5 ns transition time does not apply to the reset input line. 

    A similar query had come on OMAPL138 , which has a similar consideration

    https://e2e.ti.com/support/dsp/omap_applications_processors/int_omapl1x_dsps/f/116/t/85273.aspx

    There should've been datasheet updates to reflect this, that never happened. 

    Regards

    Mukul