Defining MSMC as NON cacheable

Yes

First check the MAR registers. They control the cache-ability of memory section.  You can disable (or enable) cache  for 4MB regions, but

If you want only part of the MSMC memory to be non-cache-able and part of it be cache-able:

You need to use the MPAX registers to logically map the part of the MSMC memory into external memory (for example) region (that might not physically exist) and then use the appropriate MAR register

Ran

Hi Ran.

I want only part of the MSMC memory non cacheable using the MPAX and MAR registers.

Please, could you tell me where is possible to find an example of it? (or if you can to advice me how to do it).

Could you tell me how the use of this new addressing will affect the MSMC performance for reading and writing compared to the use of its original address?

Thanks.

Shmuel.

Yes

Enclose is a short  presentation about how to use the MPAX and the MAR registers

If something is not clear, let's talk about it next month when I visit

Ran

1541.XMC – external memory Controller.ppt