When looking at the 'Throughput Performance Guide for KeyStone C66x Devices', it states (page 8, table 4) different performance figures for SL2 and SL3 configurations for both MSMC RAM and DDR RAM.
I understand that MSMC, accessed through its default address range, is cached only by L1D and thus considered SL2 memory. Through address remapping using the XMC MPAX and setting the appropriate MAR.PC bit(s) it can become either completely uncacheable or SL3.
I was confused by the SL3 and SL2 performance figures for DDR RAM though; as far as i know there is no configuration in which DDR RAM is only cached by L1D. I was under the impression that a 16MB region of DDR could either be not cacheable or cacheable by both L1D and L2, controlled by the MAR.PC bit. How does DDR RAM become SL2? Or is the situation in which local L2 is completely used as SRAM what is meant here?
Edit:
And another short, semi-related question: why is performance of a burst read with victim writeback on SL3 DDR RAM so much worse when it is a prefetch hit, as compared to a prefetch miss?
