AM67: TI Apps Launcher-reported DDR Bandwidth Utilization is double of what's reported using latest `k3conf` Tool

Andreas Dannenberg

Part Number: AM67
Other Parts Discussed in Thread: AM62P, AM62L

When booting the default AM67 SDK v11.0 Linux image and running the TI Apps Launcher GUI in idle mode, the "DDR Load" GUI widget shows a combined DDR load of about 1,100 MB/s (see screenshot)

However when building the latest `k3conf` tool from source (https://git.ti.com/cgit/k3conf/k3conf/) and running the tool at the same time, the displayed bandwith is approx. half of that. There seems to be a "Factor x2" discrepancy between the values reported by these tools. Why is this and which one is correct?

root@am67-sk:~# ./k3conf ddrbw
|-----------------------------------------------------------------------------------------|
| VERSION INFO                                                                            |
|-----------------------------------------------------------------------------------------|
| K3CONF           | (version v0.4-2-geaa148f built Tue May 26 05:55:19 UTC 2026)         |
| SoC              | J722S SR1.0                                                          |
| SoC identifiers  | [0x3323062e] fam: 0x0000000c base: 0x00000460                        |
| DIE-ID           | [0] 0x4B6C0000 [1] 0x00004000 [2] 0x0800fc2d [3] 0x01042d72          |
| SYSFW            | ABI: 4.0 (firmware version 0x000b '11.0.9--v11.00.09+ (Fancy Rat))') |
| DM ABI Info      | 3.0                                                                  |
| DM F/w rev       | 11.0.9                                                               |
| DM Component rev | RM/PM HAL:'v11.00.09' SCI_SERV:'MSDK.11.00.00.05+'                   |
| F/w Capabilities | 0x101: GEN DM-SPLT                                                   |
|-----------------------------------------------------------------------------------------|

|--------------------------------------------------------------------------------------------------|
| DDR instance | Read data (MiB) | Avg Read B/W (MiB/s) | Write data (MiB) | Avg Write B/W (MiB/s) |
|--------------------------------------------------------------------------------------------------|
| DDR0         | 315.484         | 315.456              | 16.725           | 16.723                |
|--------------------------------------------------------------------------------------------------|

|--------------------------------------------------------------------------------------------------|
| DDR instance | Read data (MiB) | Avg Read B/W (MiB/s) | Write data (MiB) | Avg Write B/W (MiB/s) |
|--------------------------------------------------------------------------------------------------|
| DDR0         | 532.164         | 532.117              | 7.196            | 7.195                 |
|--------------------------------------------------------------------------------------------------|

|--------------------------------------------------------------------------------------------------|
| DDR instance | Read data (MiB) | Avg Read B/W (MiB/s) | Write data (MiB) | Avg Write B/W (MiB/s) |
|--------------------------------------------------------------------------------------------------|
| DDR0         | 530.782         | 530.736              | 6.513            | 6.513                 |
|--------------------------------------------------------------------------------------------------|

|--------------------------------------------------------------------------------------------------|
| DDR instance | Read data (MiB) | Avg Read B/W (MiB/s) | Write data (MiB) | Avg Write B/W (MiB/s) |
|--------------------------------------------------------------------------------------------------|
| DDR0         | 530.825         | 530.775              | 10.625           | 10.624                |
|--------------------------------------------------------------------------------------------------|

|--------------------------------------------------------------------------------------------------|
| DDR instance | Read data (MiB) | Avg Read B/W (MiB/s) | Write data (MiB) | Avg Write B/W (MiB/s) |
|--------------------------------------------------------------------------------------------------|
| DDR0         | 532.901         | 532.843              | 10.768           | 10.767                |
|--------------------------------------------------------------------------------------------------|

|--------------------------------------------------------------------------------------------------|
| DDR instance | Read data (MiB) | Avg Read B/W (MiB/s) | Write data (MiB) | Avg Write B/W (MiB/s) |
|--------------------------------------------------------------------------------------------------|
| DDR0         | 529.692         | 529.645              | 5.634            | 5.634                 |
|--------------------------------------------------------------------------------------------------|

^C
root@am67-sk:~#

vs.

4 months ago

0 Bin Liu 4 months ago

TI__Guru**** 182096 points

Hi Andreas,

After reviewed the source code of both projects, I didn't see anything obviously off. I will try to debug both program on the EVM tomorrow to find out the reason.

0 Andreas Dannenberg 4 months ago in reply to Bin Liu

TI__Guru 70822 points

Bin, thanks. Also something might be worth considering, I've essentially been running both `k3conf` and the Apps Launcher GUI in parallel-- the only way to compare really. But this may or may not be a valid thing to do, perhaps both tools accessing (or configuring?) the perf counters are interfering with each other.

Regards, Andreas

0 Bin Liu 4 months ago in reply to Andreas Dannenberg

TI__Guru**** 182096 points

I don't think that would cause problems. Both programs configure the first two counters to be write & read counters, so should be no conflict here.

0 Bin Liu 4 months ago in reply to Bin Liu

TI__Guru**** 182096 points

Hi Andreas,

While setting up my EVM to debug the issue, I think I found the cause of the problem in the source code - the DDR burst size for J722S defined in TI Apps Launcher is 64 bytes, which is doubled of that defined in k3conf.

Ref:

https://github.com/TexasInstruments/ti-apps-launcher/blob/master/utils/perf_stats.cpp#L35

https://git.ti.com/cgit/k3conf/k3conf/tree/soc/j722s/j722s_ddr_info.c#n16

I was checking those values for AM62P device yesterday, but just realized the device ID should be J722S on the AM67x EVM.

Andreas Dannenberg said:
| K3CONF | (version v0.4-2-geaa148f built Tue May 26 05:55:19 UTC 2026) | | SoC | J722S SR1.0

0 Andreas Dannenberg 4 months ago in reply to Bin Liu

TI__Guru 70822 points

Hi Bin,

ok, so which of the tools is correct then for J722S/AM67x? Are other devices affected too?

Regards,
Andreas

0 Bin Liu 4 months ago in reply to Andreas Dannenberg

TI__Guru**** 182096 points

Hi Andreas,

In this ddrbw case, the number reported by TI Apps Launcher is correct.

James just found a couple bugs in k3conf. He has filed an internal ticket to our sw dev team.

k3conf has several bugs with respect to DDR performance measurements.

In socinfo.c there are provisions to determine the type of DDR connected to AM62L (DDR4 or LPDDR4), but the same is missing for am62x and am64x. This is necessary to ensure proper burst size is set for each of the DDR types (DDR4 = 16bytes per burst, LPDDR4 32bytes per burst) https://git.ti.com/cgit/k3conf/k3conf/tree/common/socinfo.c#n711
Burst size for am62p, am62a, and j722s should be 64 (ie, LPDDR4 Burst length * bus width = 16 * 4 bytes = 64 bytes) https://git.ti.com/cgit/k3conf/k3conf/tree/soc/am62px/am62px_ddr_info.c#n16 https://git.ti.com/cgit/k3conf/k3conf/tree/soc/am62ax/am62ax_ddr_info.c#n16 https://git.ti.com/cgit/k3conf/k3conf/tree/soc/j722s/j722s_ddr_info.c#n16

0 Andreas Dannenberg 4 months ago in reply to Bin Liu

TI__Guru 70822 points

Hi Bin,

thanks for the additional background, that is much appreciated.

Bin Liu said:
Burst size for am62p, am62a, and j722s should be 64 (ie, LPDDR4 Burst length * bus width = 16 * 4 bytes = 64 bytes) https://git.ti.com/cgit/k3conf/k3conf/tree/soc/am62px/am62px_ddr_info.c#n16 https://git.ti.com/cgit/k3conf/k3conf/tree/soc/am62ax/am62ax_ddr_info.c#n16 https://git.ti.com/cgit/k3conf/k3conf/tree/soc/j722s/j722s_ddr_info.c#n16

As for my E2E post here, are you saying that when updating the burst size for AM67x (J772S) here https://git.ti.com/cgit/k3conf/k3conf/tree/soc/j722s/j722s_ddr_info.c#n16 from 32 to 64 the DDR bandwidth test functionality in `k3conf` should be working properly?

Thanks and Regards,
Andreas

0 Bin Liu 4 months ago in reply to Andreas Dannenberg

TI__Guru**** 182096 points

Hi Andreas,

I didn't test it, but yes changing the burst size to 64 in k3conf, the DDR BW numbers should be on par with TI Apps Launcher.

+1 Andreas Dannenberg 4 months ago in reply to Bin Liu

TI__Guru 70822 points

Hi Bin,

I applied the changes you proposed to AM62A, AM62P, and AM67/J722S DDR config data structures in `k3conf` (patch attached) and re-tested the tool on the AM67/J722S EVM. The output of `k3conf ddrbw` measurements now perfectly match what's shown on the TI Apps Launcher GUI. Hope we can roll these fixes quickly into our next SDKs as well.

Thanks again for the quick resolution!

Regards,
Andreas

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_soc_2D00_am62ax_2D00_am62px_2D00_js772s_2D00_Fix_2D00_DDR_2D00_burst_2D00_size_2D00_settings.patch

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AM67: TI Apps Launcher-reported DDR Bandwidth Utilization is double of what's reported using latest `k3conf` Tool