TDA4VEN-Q1: LPDDR4 communication conditions during BOOT

Hi,

By any chance is this thread related to the following?  TDA4VEN-Q1: About the initial configuration of LPDDR4  

Furuna Yamamoto said:

When executing UART BOOT, it stops at the point where LPDDR4 communication is supposed to start.

Please tell me the conditions required for LPDDR4 communication to start during BOOT.

Is this question specific to UART boot or do you see the same issue regardless of boot method? In other words, have you tried booting from SD card or other boot methods? If so, what was the result?

In order to READ / WRITE to the LPDDR4 memory, you have to initialize the LPDDR4 interface (successfully). This means that PCB design must be adequate (proper connections, routing, etc.) and register values must be configured appropriately for the memory during driver execution.  

Furuna Yamamoto said:

Also, please let me know the LPDDR4 data rate during BOOT.

The data rate is user adjustable through the DDR configuration tool. Therefore, it would depend on your corresponding configuration used in software.

Please note that the DDR configuration tool defines two frequencies. The "LPDDR4 Boot Frequency" refers to the booting of the LPDDR4 memory. However by the time that the DDRSS software driver completes during the software bootloader stage, the frequency is at the "LPDDR4 Operating Frequency". So when you say "BOOT", I assume you are referring to the booting of the system (such as an operating system). In this case, it would correspond to how you have configured the tool input parameter "LPDDR4 Operating Frequency".

Regards,
Kevin

Hi Kevin,

Yes, this matter is related to this thread.TDA4VEN-Q1: About the initial configuration of LPDDR4  

Our current board only supports UART -> xSPI BOOT, so we have not been able to try other BOOT methods.

The LPDDR4 IF PCB pattern has been verified through transmission line simulation, so we believe there are no issues in terms of electrical characteristics.

We have tried BOOT on multiple PCB samples, but only one board can communicate with LPDDR4 normally (the other three cannot communicate).

We observed waveforms with an oscilloscope, but on PCBs that cannot communicate, DQ and DQS stay around 1.05V and do not show signs of operating (waveform data has been sent to Mr. Shibata of TI Japan).

We would like to identify the cause why communication does not start, so if there are any signals we should observe, could you please instruct us?

First, we want to distinguish whether the cause is hardware-related (e.g., assembly defect) or software-related (e.g., initialization failure).

Regards,

Hi. Kevin,

Additional question.
Regarding the switching of the LPDDR4 frequency, is my understanding correct as follows?

1. From the start of UART BOOT to the software bootloader stage (before SBL execution): LPDDR4 operating frequency (1866 MHz)

2. From the software bootloader stage (after SBL execution) to BOOT completion: LPDDR4 boot frequency (50 MHz)

3. After BOOT completion: LPDDR4 operating frequency (1866 MHz)

If we assume this is correct, we consider Phase 1 to be the most unstable.

The reason is that it has to operate at the highest frequency even though the optimal IO conditions (such as Driver Strength and ODT considered in the simulation) are not set.

Does the default IO condition mean a setting that can operate stably even under high-load, high-speed conditions like 2 RANK, 3732 Mbps?

Regards,

Hi,

Furuna Yamamoto said:

Yes, this matter is related to this thread.TDA4VEN-Q1: About the initial configuration of LPDDR4  

Based on the latest logs that were posted to the other thread, it looks like READs and WRITEs are occurring to DDR.

Furuna Yamamoto said:

but only one board can communicate with LPDDR4 normally (the other three cannot communicate).

Do you have boot logs for each tested board?

Have you tried to connect to the J722S device via JTAG and manually read / write to the LPDDR4 address range through a memory browser of an IDE (such as Code Composer Studio)?

Furuna Yamamoto said:

Additional question.
Regarding the switching of the LPDDR4 frequency, is my understanding correct as follows?

No, the LPDDR4 interface will be at the operating frequency before software can read / write to memory. The LPDDR4 boot frequency is the frequency used to setup the mode registers of the LPDDR4 memory during initialization (of the LPDDR4 memory) before training occurs. By the time the DDRSS / LPDDR4 initialization is complete in the software bootloader, the LPDDR4 frequency is set to the operating frequency. It is at this time that software can begin reading and/or writing to LPDDR4 memory.

Furuna Yamamoto said:

Does the default IO condition mean a setting that can operate stably even under high-load, high-speed conditions like 2 RANK, 3732 Mbps?

The default input parameters of the DDR configuration tool are setup to work with the TI J722S EVM, which has a dual rank memory. 

Regards,
Kevin