AM335 Ethernet Interupt pacing implementation??

Yes, interrupt pacing has been implemented.  However, the interrupt pacing logic was accidently not connected directly to the ARM Cortex-A8 interrupt controller.

These interrupts can be connected to ARM Cortex-A8 interrupt controller by re-routing them through two of the AM335x timers.  A description of this problem and a workaround will be released in the next version of the AM335x Silicon Errata.

Regards,
Paul  

peaves, please could you clarify whether Ethernet interrupt pacing is expected to work on current AM335x silicon?

I've searched the TI forum, perused the datasheet and errata, but am still unsure what the answer is.

Quoting you above: "Yes, interrupt pacing has been implemented.  However, the interrupt pacing logic was accidently not connected directly to the ARM Cortex-A8 interrupt controller."

Another post states: "Note that Interrupt pacing is not directly supported for CPSW interrupts due to the Silicon errata Advisaory 1.0.9"

Revision F of the Errata has: "If (...) interrupt pacing is required, the following workaround must be implemented"

The reason I'm asking is that we have successfully implemented the workaround described in Advisory 1.0.9, but when we try to enable interrupt pacing we don't see any difference in the interrupt rate.

To configure interrupt pacing, we:

• Set C0_RX_IMAX and C0_TX_IMAX to 2 (maximum of 2 interrupts/ms),
• Enable interrupt pacing by setting bits 16-21 in INT_CONTROL, and
• Set the INT_PRESCALE value to 1 (the idea being to apply maximum throttling in order to observe the effect).

This is similar to what the current Linux driver does, however we see no change in the interrupt rate in any of our tests.

Are there any additional steps that need to be taken when interrupts have been re-routed as per the advisory?

Best regards,
Carsten

Hi Carsten,

Carsten Hansen said:

please could you clarify whether Ethernet interrupt pacing is expected to work on current AM335x silicon?

According to Table 4 in AM335X Errata Rev. F, Advisory 1.0.9 is valid only for Silicon Revision 1.0.

And here is a link to the Linux CPSW Driver's Guide: processors.wiki.ti.com/.../Linux_Core_CPSW_User's_Guide

Thanks Biser,

Say if you have implemented Advisory 1.0.9 regardless, would interrupt pacing as documented in the datasheet, and implemented in the Linux driver, be expected to work?

Best regards,
Carsten

I can't say, I'm not much of a SW expert. I have asked the experts to answer this.

Biser,

Reviewing the code and the errata it became clear to me that we don't need the 1.0.9 workaround anymore, so my original question is no longer relevant.

Thanks again for your time,
Carsten