Part Number: AM62A7
Other Parts Discussed in Thread: SK-AM62A-LP
Hi,
Im using an AM62A-LP dev board and trying to build an ultra-low-latency H.264 encode pipeline on (AM62A7 (SR1.0), SK-AM62A-LP EVM, Processor SDK 11.00.09.04 (kernel 6.12.24-k3), WAVE521C VPU fw rev 363254) and need to drive the encoder's source sub-frame sync so it consumes the source frame buffer progressively (per macroblock-row) instead of waiting for the whole frame. Specifically:
1. W5_CMD_ENC_SRC_OPTIONS (W5_REG_BASE+0x128) — confirm bit layout: bit0=sub_frame_sync_enable, bit1=mode (0=wire, 1=register). For AM62A, is the wire-based source-sync signal physically connected to the VPU, or is register-based the only supported mode?
2. W5_ENC_PIC_SUB_FRAME_SYNC_IF (W5_REG_BASE+0x300) — full handshake for register-based mode: what value does the host write (row count? CTU-row count? source write-pointer?), at what point relative to W5_ENC_PIC, and what/where does the firmware signal back (which register/interrupt) as it consumes rows?
3. Minimum encode picture height — the driver enforces 128; what does the WAVE521C firmware actually support (can it encode a 16- or 32-row picture, i.e. 1–2 MB rows)?
4. OPT_CHANGE_PARAM — the per-frame parameter-change path (e.g. GDR/intra-refresh position, QP) for our zero-latency profile.
5. Any reference / example code for source sub-frame sync (the mainline driver and the public ChipsnMedia/V4L2_TI repo define these registers but never drive them).
Finally what is the correct method to gain acccess to the Wave521 API reference/programming guide?
Thanks.
