Part Number: TDA4VEN-Q1
Other Parts Discussed in Thread: 4428, AM62P
We are doing falcon mode between R5F MCU to A53 and would like to keep the OLDI peripheral (and it's clocks) from being reset during kernel initialization before the tidss driver gets loaded.
I've enabled DSS0 with dev-data.c and clk-data.c
After the built-in k3 driver runs, the OLID output will be 300MHz instead of 71MHz, causing the output to stop working correclty.
I see that perhaps because I've directly connected the dss0 fck to hsdiv0_16fft_main_16_hsdivout0_clk, when the a53 kernel inits k3, it resets the OLDI register to 2100MHz, so divided by 7, is 300MHz.
Either I need to match the final clock configuration with my dev-data.c and clk-data.c or I need to update the k3 default behavior to skip initializing these clocks.
Does TI have a recommendation for this feature?
Note that 300MHz happens before I modprobe the tidss module, so it's during the most basic k3 init.
After the modprobe, I get normal behavior, but via a different clock tree path.
Thanks. See the patch attached for the u-boot r5f SPL changes:
diff --git a/arch/arm/mach-k3/r5/j722s/clk-data.c b/arch/arm/mach-k3/r5/j722s/clk-data.c
index cb3d864c..9ec8c7da 100644
--- a/arch/arm/mach-k3/r5/j722s/clk-data.c
+++ b/arch/arm/mach-k3/r5/j722s/clk-data.c
@@ -166,6 +166,11 @@ static const struct clk_data clk_list[] = {
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
+ CLK_FIXED_RATE("dss0_func_clk", 72400000, 0),
+ CLK_FIXED_RATE("dss0_vp0_clk", 72400000, 0),
+ CLK_FIXED_RATE("dss0_vp1_clk", 72400000, 0),
+ CLK_FIXED_RATE("dss_oldi0_clk", 72400000, 0),
+ CLK_FIXED_RATE("dss_oldi1_clk", 72400000, 0),
CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
@@ -174,6 +179,7 @@ static const struct clk_data clk_list[] = {
CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
CLK_PLL("pllfracf2_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
+ CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_16_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x690000, 0, 506800000),
CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
CLK_DIV("pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
@@ -195,6 +201,7 @@ static const struct clk_data clk_list[] = {
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
+ CLK_DIV("hsdiv0_16fft_main_16_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
@@ -342,6 +349,11 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
DEV_CLK(170, 2, "board_0_tck_out"),
DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(186, 6, "hsdiv0_16fft_main_16_hsdivout0_clk"),
+ DEV_CLK(186, 0, "dss0_vp0_clk"),
+ DEV_CLK(186, 2, "dss0_vp1_clk"),
+ DEV_CLK(243, 0, "dss_oldi0_clk"),
+ DEV_CLK(244, 0, "dss_oldi1_clk"),
};
const struct ti_k3_clk_platdata j722s_clk_platdata = {
diff --git a/arch/arm/mach-k3/r5/j722s/dev-data.c b/arch/arm/mach-k3/r5/j722s/dev-data.c
index 5f7e2a44..0371de1c 100644
--- a/arch/arm/mach-k3/r5/j722s/dev-data.c
+++ b/arch/arm/mach-k3/r5/j722s/dev-data.c
@@ -19,6 +19,7 @@ static struct ti_pd soc_pd_list[] = {
[1] = PSC_PD(3, &soc_psc_list[0], &soc_pd_list[0]),
[2] = PSC_PD(4, &soc_psc_list[0], &soc_pd_list[1]),
[3] = PSC_PD(13, &soc_psc_list[0], &soc_pd_list[0]),
+ [4] = PSC_PD(21, &soc_psc_list[0], &soc_pd_list[0]),
};
static struct ti_lpsc soc_lpsc_list[] = {
@@ -36,6 +37,9 @@ static struct ti_lpsc soc_lpsc_list[] = {
[11] = PSC_LPSC(72, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[7]),
[12] = PSC_LPSC(73, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[11]),
[13] = PSC_LPSC(74, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[12]),
+ [14] = PSC_LPSC(91, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[7]),
+ [15] = PSC_LPSC(94, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[7]),
+ [16] = PSC_LPSC(95, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[7]),
};
static struct ti_dev soc_dev_list[] = {
@@ -57,6 +61,9 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(170, &soc_lpsc_list[11]),
PSC_DEV(177, &soc_lpsc_list[12]),
PSC_DEV(55, &soc_lpsc_list[13]),
+ PSC_DEV(186, &soc_lpsc_list[14]),
+ PSC_DEV(243, &soc_lpsc_list[15]),
+ PSC_DEV(244, &soc_lpsc_list[16]),
};
const struct ti_k3_pd_platdata j722s_pd_platdata = {
