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Booting from XIP NOR

Stephen Hicks
Intellectual 470 points
Let me describe in detail our current stumbling block:
- Our board is configured for XIP (execute in place) boot and so we believe that the Integra wants to see code in sector 0
- Our understanding is that the Integra only enables A0-A11 of the flash on boot -- this means that whatever we are going to do in the first bootloader, it needs to be done in 2kB of memory
- Upon boot, our understanding is that the Integra will map the flash to 0x0800_0000.  After boot, the part will need to move to 0x1000_0000 so as not to obscure the second half of the flash part

The question is: what mechanism do we need to use to make this happen?  Should we compile uBoot to run at 0x1000_0800 (2kB into the flash) and write a simple C program to adjust the GPMC parameters and then start uBoot from that location (this C program would then be squirted into the flash at sector 0)?  Is there already something written to do this?
  • 0
    TI__Genius 15310 points

    Stephen,

    Please pay attention to the XIP Boot note below.  I will send your other questions to our expert.

    In this device, during XIP Boot process, the ROM code does not multiplex high order address lines gpmc_a[27:13] to their address functions although the external memory device generally needs to see logic "0" on its higher order address bits to correctly address memory.  Many of the high order address pads default to internal pull-down (IPD) active, however some pins default to internal pull-up (IPU) active and therefore will need to be driven or pulled low by external hardware for duration of XIP boot operation.  See section XIP (NOR) Boot Options of Device Configurations chapter in the Device Data Manual for specific details about how the ROM configures pins for various XIP boot options.  For those pins not specifically configured by the ROM, consult Data Manual  table  X-X “PINCNTL Registers MUXMODE Functions” to determine default pull state (IPD/IPU) of each address pin used gpmc_a[27:13]. 

    Note that to counteract an internal pull up one should typically use an external 1k ohm pulldown resistor.

    BR,

    Viet

  • 0 in reply to Viet Dinh
    TI__Guru*** 125430 points

    In terms of the implementation I believe you'll want to simply link all the u-boot code to the final address.  The lowlevel init code in u-boot is position independent, i.e. it is assembly code, uses relative branches, etc. This is the same code talked about here:

    http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_PSP_U-Boot#NOR_Support

    You should be able to change the GPMC base address in that same code.  I believe u-boot is setup such that it relocates itself to DDR in any case.  Is that how you currently have it setup?

    Hopefully this helps out a little bit.  I'm on vacation and won't be available to answer any more questions on this issue until next week.  I just wanted to give a quick pointer if possible.

    Best regards,
    Brad

  • 0 in reply to Viet Dinh
    Intellectual 470 points

    Can you provide a link to the "device data manual."  I can't seem to find this document.  I've been using the data sheet (SPRS680B) and the technical Reference Manual (SPRUGX9).

    Thanks.

  • 0 in reply to Stephen Hicks
    TI__Genius 15310 points

    Stephen,

    Sorry for confusion.  Data sheet is Data Manual.

    BR,

    Viet