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Enabling prefetch for the SL2 of the C6472

Miguel Aguilar
Intellectual 855 points
Other Parts Discussed in Thread: SYSBIOS

Hi,

I am working with the C6472, but I want to know how to be sure that the prefetch for the SL2 is enabled, so far I have not found any documentation how to do it with SYSBIOS or CSL?

Thanks,

Miguel

  • 0
    TI__Mastermind 32475 points

    Miguel,

    My understanding is that for this device (c6472), it comes with prefetch for shared memory automatically on. 
    This is not something that can be configured.

    Judah

  • 0 in reply to judahvang
    Intellectual 855 points

    Hi Judah,

    According with this user guide of the SMC there are register to enable the prefetch: http://www.ti.com/lit/ug/sprueg5d/sprueg5d.pdf.

    The problems is that I implemented fifos in shared memory for core to core communication and I tested the fifos both in SL2 and DDR2, but for some reason the when I use the DDR2 I get better performance than when I use SL2.  The test application that I am using is a ring topology where all the 6 cores are involved, then there is simultaneous access to the SL2 or to DDR2, because there are 6 fifos in total in the same memory.

    To be more specific the difference in performance is while I am executing the cache coherence routines (wb and inv).

    Any idea why the SL2 could be slower than the DDR3 even if I am using the same code for the FIFO implementation?

    Thanks,

    Miguel

  • 0 in reply to Miguel Aguilar
    TI__Mastermind 32475 points

    Miguel,

    I know BIOS does not currently support this feature the c6472.  I will file an enhancement request but I don't know if/when it will be fixed.
    I know in the C66xx devices, we do support a pre-fetchable feature but I think its implementation is a bit different.

    I don't know why SL2 would be slower than DDR2/3.  That definitely does not sound right to me.  We've done some IPC benchmarks for C6472
    and I've never seen the case where SL2 is slower than DDR.  Could something else be causing the bottleneck?

    When you have things in DDR, is the data being cached also?  Are you having to perform cache coherence for DDR?  If you don't, that could explain the difference.

    As for the prefetch, I think you could add it to your app.

    The base address of the SMC starts for core0 at:  02C20000 - 02C23FFF (Note each core's SMC base addr is different.  See page 12 of http://www.ti.com/lit/ds/sprs612g/sprs612g.pdf)

    You just need  to set the base address for each core to all ones to enable pre-fetch.  see page 22 of http://www.ti.com/lit/ug/sprueg5d/sprueg5d.pdf

    Judah