System bus load to high or DMA conflicts?

Hi all,

in our application we are using 3 peripherals with DMA transfers:

• SPI clocked with 10MHz
• UPP clocked with 10 MHz
• VPIF clocked with 27 MHz

now if all 3 functionalites are enabled at once, we get strange behaviours with the received data arrived from either SPI or UPP. If only

1. SPI and UPP or
2. UPP and VPIF or
3. VPIF and SPI

are used exclusevily it seems to work good. Can it be that the internal bus load gets somehow to high if  all 3 peripherals are used at once? Or is this not possible? If so, what can be done to avoid this? Our burst sizes are as follow:

UPP - 64 bytes DMA burst size

VPIF - 32 bytes DMA burst size

SPI - see spi_edma driver.

Also it seems that if the SPI clock is decreased to 2 MHz the system seems to run more stable, which would support the assumption.

Your answers and knowledge on this issue are very appreciated. The whole application runs on the C6748 without using the ARM-core. If you need additional information please let me know.

Thanks,
Steve