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TMS320F28377S: eCAP SyncIn delayed

Stephane Bonnot
Prodigy 70 points

Part Number: TMS320F28377S

Hello,
I curently use eCAP module to mesasure phase shift between the ePWM CTR = 0 and an external signal comming from a GPIO.

The ePWM SyncOut signal is routed to eCAP SyncIn signal in order to reset the eCAP counter. the external signal (from GPIO) is routed to the eCAP input. The rising edge of the external signal triggers a capture in CAP1 register in continuous mode.

To test this design, I have loop back the ePWM output A used to reset the eCAP counter, to the eCAP external signal input. This, in order to have a fixed phase shift measurement that ease the software design and debug. (See schem in attached file)eCAP_sync.png

This design work fine, except a constant offset of +10 SYSCLK in mesasurement (CAP1 register).

The eCAP CAP1 expected value is:
CAP1 = (ePWM CMPA * 2) - 4 
* ePWM CMPA * 2 : because ePWM CMPA is used to force ePWM output A at high level, * 2 is du to ePWM clock prescaler configuration.
* - 4 : Becaue it is the ePWM SYNCOUT propagation signal delay.

Instead of this value, I read (CMPA * 2) + 6. A total diference of 10 SYSCLK.

I try to find a response in TMS320F2837xS TRM and TI forums, that I unfortunately haven't found. 

Questions:
Is there a technical explaination of this diff?
Is my software design faulty?
Is my expected value in CAP1 register faulty?

  • 0
    TI__Intellectual 990 points

    Hi,

    Can u provide me the software configuration and code for capturing this delay?

    Thanks,

    Divesh

  • 0 in reply to Divesh Dang 18431815
    Prodigy 70 points

    Hello.
    Here is the software used.

    Note:
    * This software is extracted from original software and has neither been compiled nor tested.
    * The loopback explained above is a physical loopbak. ePMW1 output A is physically (wired) loopbaked to eCAP input pin (GPIO0x)
    * If an internal loopback is used (eCAP input is routed with INPUT X-BAR to ePWM1 outputA) the timestamp offset is 11 (instead of 10 with physical loopback).

    PhaseShift.zip

  • 0 in reply to Stephane Bonnot
    TI__Intellectual 990 points

    Hi,

    Thanks for you reply. I will try to provide some explanation within two-three days.

    Thanks,

    Divesh

  • 0 in reply to Divesh Dang 18431815
    TI__Intellectual 990 points

    Hi,

    The time difference between syncout pulse ( generated by ePWM) and rising edge of EPWMx_A output should have been less than 1000 SYSCLK cycles as the SYNOUT pulse takes some time to propagate to eCAP and for counter to be loaded with phase value ( it is zero in your case). It appears that INPUTXBAR is adding some delay to the EPWMx_A pulse. This is the reason why you are observing that measured time is more than expected time. To verify this, I have looped in design expert. 

    Your software configurations are correct. The CAP1 registers are also not giving incorrect result. You need to compensate this with the help of software.

    Once I get some results from design team, I will notify you. 

    Thanks,

    Divesh