DRA821U: DRA821 supported MAC interfaces

P B,

DRA821 supports 1G and 2.5G SGMII on all ports such that the total baud rate can be considered as 10G (Quad x 2.5G).

The USXGMII 10G is supported only on port 1 of the CPSW and not on all ports. 

and as you have pointed out, the QSGMII 5Gb combines 4 internal CPSW ports on a single SERDES lane. 

Thanks but this is still not clear to me.

You said that any of the ports supports 1 and 2,5 SGMII so that it can be considered 10G (Quad 2,5G) but do they use the same Serdes or does each port use its own serdes? 

There is a difference between Quad 2,5G where all ports share the same serdes vs each port uses its own Serdes.

I understand that QSGMII combines 4 ports into a single Serdes lane but QSGMII suports max 1G not 2,5G

Please look again on the description from LS1028 
"10G-QXGMII allows 4 TSN Switch MACs to share a single SerDes lane and negotiate speeds up to 2.5 Gbps per
link. It is connected to the 4 switch ports and supports each port negotiating rates of 10M, 100M, 1G, or 2.5G."

Having this in mind - is it possible to share a single Serdes lane between 4 ports of CPSW where each port can negotiate up to 2,5G?

PB,

There is only a single SERDES on DRA821 with 4 lanes and each lane can support 2.5G and be assigned to 4 different CPSW ports.

Thanks ShreyasRao  that you're trying to help me but I I need to be 100% sure that we are on the same page. 

"There is only a single SERDES on DRA821 with 4 lanes and each lane can support 2.5G and be assigned to 4 different CPSW ports." - in this setup each port will use its own Serdes Lane am I right?

I'm asking because there is a huge difference between 

- all ports using the same Serdes lane (QSGMII 1Gb max)

- each port use its own Serdes lane and supports up to 2,5Gb 

I would like to get just a simple "yes", "no" answer.

On LS1028A Switch can be configured so that each of its port supports up 2,5Gb but all ports use THE SAME Serdes Lane.

Can I do the same on DRA821? Is it possible to configure CPSW so that each switch port supports speed up to 2,5Gb but each port share the same Serdes Lane? 

This mode is is described in DRA821 datasheet as:
"QSGMII mode combines all four internal ports of the CPSW onto a single SERDES lane. Each port in this mode operates at 1-Gb
full duplex". but the speed the doc mentions is 1Gb not 2,5Gb.

You said "DRA821 supports 1G and 2.5G SGMII on all ports such that the total baud rate can be considered as 10G (Quad x 2.5G)." - but will it work the same way as QSGMII but with max speed 2,5Gb per port? Will this mode use 4 Serdes Lane or Single, shared Serdes Lane?

Hi PB, 

Yes, I am in the same page on this.

To clarify:

P B said:

"There is only a single SERDES on DRA821 with 4 lanes and each lane can support 2.5G and be assigned to 4 different CPSW ports." - in this setup each port will use its own Serdes Lane am I right?

Yes, each port of the CPSW is assigned to its own SERDES lane.

P B said:

This mode is is described in DRA821 datasheet as:
"QSGMII mode combines all four internal ports of the CPSW onto a single SERDES lane. Each port in this mode operates at 1-Gb
full duplex". but the speed the doc mentions is 1Gb not 2,5Gb.

Yes, QSGMII 5G is supported with 1Gx4 CPSW ports combined onto one SERDES lane. 2.5G x 4 Ports has not been validated internally to claim support on single SERDES lane. You would need to use per lane, per port for the 2.5G.

Please let me know on how you would proceed on this. 

Thanks. 

Regarding this:

"Yes, QSGMII 5G is supported with 1Gx4 CPSW ports combined onto one SERDES lane. 2.5G x 4 Ports has not been validated internally to claim support on single SERDES lane. You would need to use per lane, per port for the 2.5G."

What do you mean that you did not validate this internally to claim support on a single lane? Are you going to do so in the nearest future or not? Is this a silicon limitation or lack of support in sw?

Sorry that I'm perhaps too pushy, but I already have an existing design of a carrier board that has a 10G QXGMII phy (4 ports using shared, single Serdes lane up to 2,5Gb for each port), and I'm trying to find out whether or not I can make a SoM with DRA821 that will be compatible with this carrier board. If not I will have to replace the carrier board's phy, that's why I'm asking all these questions.

P B said:

What do you mean that you did not validate this internally to claim support on a single lane? Are you going to do so in the nearest future or not? 

Unfortunately, there is no plan to support this currently.