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AM6442: LPDDR4 output slew rate

Kien
Expert 4546 points

Part Number: AM6442

Hi Champs,

When we do the LPDDR4 compliance test, we have some issue with the memory output slew rate.

The slew rate we measure is around 3~4 V/ns. However, the requirement from the standard is 3.5 V/ns(for single ended signals) and 7/ns(for differential signals).

Do you have any suggestion on improving this slew rate?

Also, the standard does not clearly specify the VOH/VOL. Do you have any recommended value that we shall use as the threshold for measurement?

 

Regards,

Kien

  • 0
    TI__Guru* 94981 points

    Kien, which signals are failing output slew rate?  

    You should be able to use VOH=VDDQ/3 and VOL=0.1*VDDQ

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 30 points

    Thanks for your suggestion, James!

    We are failing at both DQ single-ended and DQS differential slew rate.

    Also, there is always a step in the rising/falling edge, is this due to the impedance mismatch?

    We are currently configuring the MCU DDR setting as:

    Drive Strength: Pull-Down (PDDS) = RZQ/6(40ohm)

    Termination: DQ ODT (FSP2)  = RZQ/6(40ohm)

    Termination: SOC ODT (FSP2)  = RZQ/5(48ohm)

    Could you give us any suggestion to improve the waveform quality?

    DQ0 waveformDQS0 waveform

  • 0 in reply to QIAO ZHANG
    TI__Guru* 94981 points

    Yes, the step is most likely due to impedance mismatch. 

    Did you do any board simulations on the design?  This would usually give you the best configuration settings for drive strength and termination

    If you did not do any board level SI simulations, you may have to try different settings.  

    Were these waveforms taken during read or write cycle?  

    If during read, adjust:

    DRAM driver and Processor ODT

    If during write, adjust:

    Processor driver and DRAM ODT

    also, can you provide the full DDR Configuration from the tool (.syscfg)

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 30 points

    These are the waveforms from the read cycles.

    Here is the full DDR Configuration from the tool:

    Sysconfig_settings_info.zip

    We have done SI simulation based on this setup, but the SI Engineer has left the project.

    The IBIS models are provided by TI. Can you help us to check the ODT setting used for the Read/Write in the SI simulation?

  • 0 in reply to QIAO ZHANG
    TI__Guru* 94981 points

    Based on the setup, it shows 40ohm driver and 80ohm ODT for both read and write, but you don't have that set up in the DDR configuration file.  

    However, i've never seen 80ohm ODT for this configuration.  Can you try changing all processor DQ ODT to 40ohm by changing the following in the DDR configuration tool

    Termination: DQ ODT (FSP2)  = RZQ/6(40ohm)

    Termination: SOC ODT (FSP2)  = RZQ/6(40ohm)

    Regards,

    James