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AM1808 won't boot

Samuel Rule
Prodigy 235 points

Other Parts Discussed in Thread: AM1808

I am working with an AM1808 on a custom board that seems to be in a funny state that won't fully boot.  I am building my application with gcc. When I try to Run->Load->Load Program... it copies my application about 75% of the way and then there is an error stating it can't copy to some DDR address.  I tried running the gel script Core_100MHz_mDDR_102MHz. Then I am able to fully copy the application, but it gets stuck in a loop in ROM. See the green lines in the disassembly.

I also tried reducing the size of my application to almost nothing.  In that case I can actually step into main, but I can only run about 2 lines of code before it hangs.

Any ideas on what I can look for? Registery settings?

Sam

  • 0
    Prodigy 235 points

    OK, now I have done it.  I ended up moving to a different board because the first one wasn't working.  I resumed the work I was doing on the first board on the second board which was trying to configure the AIS and copy it to the serial flash.  Well, after doing that, my second board will no longer boot.  My guess is that something in the AIS configured image was wrong and being loaded before the jtag connects or conflicting with something in the gel file.  

    Is there any way to prevent the device from even looking at the SPI0 on boot and just doing what the jtag/gel file says to do?

  • 0 in reply to Samuel Rule
    TI__Guru*** 125430 points

    A couple options are:

    1. Overdrive the boot pins to change to a different boot mode (e.g. blue wire to power/ground on appropriate pads).
    2. Perform a "system reset" on the device which should un-do whatever is happening on the SPI boot.  To do so:
    1. Right click on the ARM926 core in the "Debug" window and enable the "Halt on Reset" option.
    2. Select Run -> Reset -> System Reset.  Now you will have a full hardware reset of the device and PC will be pointing to the ROM entry point.

    Here's a screenshot of the "halt on reset" option from a different device in case that step wasn't clear:

    Also, when you connect and things are in a bad state there are a few things you can do:

    1. Check along the bottom bar in CCS.  It gives information such as what mode the ARM is operating (Supervisor, User, Abort, etc).  If you're in abort mode, that might give a clue as to the issue.
    2. There is a gel file which you can load to help diagnose issues.  Take the resulting output and copy into a txt file and attach to the post.  It might give some clues as to what's happening. http://processors.wiki.ti.com/index.php/OMAP-L1x_Debug_Gel_Files
    3. Generally speaking, make it simpler!  For example, when you are creating your AIS formatted file, are you using a bunch of AIS options (DDR config, PSC config, etc.)?  Try making an image without those options and put a spin loop right at the beginning.  See if you can at least consistently get to that point.
  • 0 in reply to Samuel Rule
    TI__Expert 8890 points

    Samuel,

    Could you post your AIS file so we can review it?  That may be the fastest way to diagnose what has gone wrong.  If your AIS file is very large or you don't want to post it for other reasons, maybe we could try creating a simpler AIS file as an experiment (i.e. a do-nothing application with a while(1) loop to trap the PC after boot).  The two most likely causes of the problem you describe are:

    • Application sections are being loaded to external memory (i.e. DDR), but the AIS file does not include the necessary commands to configure EMIF.  You can fix this by checking "Configure DDR" in the AISgen tool and navigating to the DDR tab to specify appropriate configuration values.
    • The wrong boot mode was selected in the AISgen tool.  This is a particular concern if you select a NOR boot mode in the tool and attempt to boot from a different memory type, like SPI flash.

    Also, for more help diagnosing the bootloader status when it gets trapped in the ROM, you can try using the debug GEL files provided on the following wiki page:

    http://processors.wiki.ti.com/index.php/OMAP-L1x_Debug_Gel_Files

    This can be a big help determining what the ROM thinks has happened (i.e. error status, boot mode, etc.).

    Hope this helps.

  • 0 in reply to Brad Griffis
    Prodigy 235 points

    Thanks for the help.  The halt on reset was just what I needed.  I was able to get just enough of the application going to erase what was in the serial flash.  

    I agree with keeping it simple and ramping up, but even then I am bound to make a mistake and needed a way fix my boards and try again.

  • 0 in reply to Joe Coombs
    Prodigy 235 points

    Joe,

    I cannot post the AIS binary.  I tried to create AIS settings that I thought would mimic the default GEL file.  Here are the settings for the DDR I tried, unfortunately I did not save the settings or try capture the screens.

    Here is what the debug GEL output:

    ---------------------------------------------
    ARM9_0: GEL Output: |             Device Information            |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
    ARM9_0: GEL Output: DEV_INFO_01 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_02 = 0x0000000A
    ARM9_0: GEL Output: DEV_INFO_03 = 0x00000013
    ARM9_0: GEL Output: DEV_INFO_04 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_05 = 0x000003E0
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-6438272-7-45-26
    ARM9_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 3,0,0,12072
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_17 = 0x00030003
    ARM9_0: GEL Output: DEV_INFO_18 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_19 =ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 0ARM9_0: GEL Output: 
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_20 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_21 = 0x00000000
    ARM9_0: GEL Output: DEV_INFO_22 = 0x30303864
    ARM9_0: GEL Output: DEV_INFO_23 = 0x3830306B
    ARM9_0: GEL Output: -----
    ARM9_0: GEL Output: DEV_INFO_24 = 0x0701A02D
    ARM9_0: GEL Output: DEV_INFO_25 = 0x00623D80
    ARM9_0: GEL Output: DEV_INFO_06 = 0x00000080
    ARM9_0: GEL Output: DEV_INFO_26 = 0x5E500003
    ARM9_0: GEL Output: 

    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: |               BOOTROM Info                |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: ROM ID: d800k008 
    ARM9_0: GEL Output: Silicon Revision 2.1
    ARM9_0: GEL Output: Boot pins: 10
    ARM9_0: GEL Output: Boot Mode: SPI0 Flash
    ARM9_0: GEL Output: 
    ROM Status Code: 0x00000009 
    Description:ARM9_0: GEL Output: Invalid AIS keyword
    ARM9_0: GEL Output: 
    Program Counter (PC) = 0xFFFD45E0
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: |              Clock Information             |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: PLLs configured to utilize crystal.
    ARM9_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: NOTE:  All clock frequencies in following PLL sections are based
    ARM9_0: GEL Output: off OSCIN = 24 MHz.  If that value does not match your hardware
    ARM9_0: GEL Output: you should change the #define in the top of the gel file, save it,
    ARM9_0: GEL Output: and then reload.
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: |              PLL0 Information             |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: PLL0_PREDIV = 24 MHz
    ARM9_0: GEL Output: PLL0_PLLOUT = 600 MHz
    ARM9_0: GEL Output: PLL0_PLLOUT_POSTDIV = 300 MHz
    ARM9_0: GEL Output: PLL0_PLLEN = 24 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK1 = 24 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK2 = 12 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK3 = 8 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK4 = 6 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK5 = 8 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK6 = 24 MHz
    ARM9_0: GEL Output: PLL0_SYSCLK7 = 4 MHz
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: |              PLL1 Information             |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: PLL1_PLLOUT = 528 MHz
    ARM9_0: GEL Output: PLL1_PLLOUT_POSTDIV = 264 MHz
    ARM9_0: GEL Output: PLL1_PLLEN = 24 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK1 = 24 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK2 = 24 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK3 = 24 MHz
    ARM9_0: Output: 	Memory Map Setup Complete.
    ARM9_0: Output: 	---------------------------------------------
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: |              PSC0 Information             |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output:  1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: Module 0:	EDMA3CC (0)        STATE = 0
    ARM9_0: GEL Output: Module 1:	EDMA3 TC0          STATE = 0
    ARM9_0: GEL Output: Module 2:	EDMA3 TC1          STATE = 0
    ARM9_0: GEL Output: Module 3:	EMIFA (BR7)        STATE = 0
    ARM9_0: GEL Output: Module 4:	SPI 0              STATE = 3
    ARM9_0: GEL Output: Module 5:	MMC/SD 0           STATE = 0
    ARM9_0: GEL Output: Module 6:	AINTC              STATE = 3
    ARM9_0: GEL Output: Module 7:	ARM RAM/ROM        STATE = 3
    ARM9_0: GEL Output: Module 9:	UART 0             STATE = 0
    ARM9_0: GEL Output: Module 10:	SCR 0 (BR0/1/2/8)  STATE = 3
    ARM9_0: GEL Output: Module 11:	SCR 1 (BR4)        STATE = 3
    ARM9_0: GEL Output: Module 12:	SCR 2 (BR3/5/6)    STATE = 3
    ARM9_0: GEL Output: Module 13:	PRUSS              STATE = 0
    ARM9_0: GEL Output: Module 14:	ARM                STATE = 3
    ARM9_0: GEL Output: Module 15:	DSP                STATE = 0
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: |              PSC1 Information             |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: State Decoder:
    ARM9_0: GEL Output:  0 = SwRstDisable (reset asserted, clock off)
    ARM9_0: GEL Output:  1 = SyncReset (reset assered, clock on)
    ARM9_0: GEL Output:  2 = Disable (reset de-asserted, clock off)
    ARM9_0: GEL Output:  3 = Enable (reset de-asserted, clock on)
    ARM9_0: GEL Output: >3 = Transition in progress
    ARM9_0: GEL Output: 
    ARM9_0: GEL Output: Module 0:	EDMA3CC (1)        STATE = 0
    ARM9_0: GEL Output: Module 1:	USB0 (2.0)         STATE = 0
    ARM9_0: GEL Output: Module 2:	USB1 (1.1)         STATE = 0
    ARM9_0: GEL Output: Module 3:	GPIO               STATE = 0
    ARM9_0: GEL Output: Module 4:	UHPI               STATE = 0
    ARM9_0: GEL Output: Module 5:	EMAC               STATE = 0
    ARM9_0: GEL Output: Module 6:	DDR2 and SCR F3    STATE = 0
    ARM9_0: GEL Output: Module 7:	MCASP0 + FIFO      STATE = 0
    ARM9_0: GEL Output: Module 8:	SATA               STATE = 0
    ARM9_0: GEL Output: Module 9:	VPIF               STATE = 0
    ARM9_0: GEL Output: Module 10:	SPI 1              STATE = 0
    ARM9_0: GEL Output: Module 11:	I2C 1              STATE = 0
    ARM9_0: GEL Output: Module 12:	UART 1             STATE = 0
    ARM9_0: GEL Output: Module 13:	UART 2             STATE = 0
    ARM9_0: GEL Output: Module 14:	MCBSP0 + FIFO      STATE = 0
    ARM9_0: GEL Output: Module 15:	MCBSP1 + FIFO      STATE = 0
    ARM9_0: GEL Output: Module 16:	LCDC               STATE = 0
    ARM9_0: GEL Output: Module 17:	eHRPWM (all)       STATE = 0
    ARM9_0: GEL Output: Module 18:	MMC/SD 1           STATE = 0
    ARM9_0: GEL Output: Module 19:	UPP                STATE = 0
    ARM9_0: GEL Output: Module 20:	eCAP (all)         STATE = 0
    ARM9_0: GEL Output: Module 21:	EDMA3 TC2          STATE = 0
    ARM9_0: GEL Output: Module 24:	SCR-F0 Br-F0       STATE = 3
    ARM9_0: GEL Output: Module 25:	SCR-F1 Br-F1       STATE = 3
    ARM9_0: GEL Output: Module 26:	SCR-F2 Br-F2       STATE = 3
    ARM9_0: GEL Output: Module 27:	SCR-F6 Br-F3       STATE = 3
    ARM9_0: GEL Output: Module 28:	SCR-F7 Br-F4       STATE = 3
    ARM9_0: GEL Output: Module 29:	SCR-F8 Br-F5       STATE = 3
    ARM9_0: GEL Output: Module 30:	Br-F7 (DDR Contr)  STATE = 3
    ARM9_0: GEL Output: Module 31:	L3 RAM, SCR-F4, Br-F6 STATE = 3
  • 0 in reply to Samuel Rule
    TI__Guru*** 125430 points

    Samuel Rule said:
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output: | PLL1 Information |
    ARM9_0: GEL Output: ---------------------------------------------
    ARM9_0: GEL Output:
    ARM9_0: GEL Output: PLL1_PLLOUT = 528 MHz
    ARM9_0: GEL Output: PLL1_PLLOUT_POSTDIV = 264 MHz
    ARM9_0: GEL Output: PLL1_PLLEN = 24 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK1 = 24 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK2 = 24 MHz
    ARM9_0: GEL Output: PLL1_SYSCLK3 = 24 MHz

    Uncheck the "Use direct clock from PLL1" option in AISgen.  You're clocking your DDR at 24 MHz!

    Samuel Rule said:
    ARM9_0: GEL Output: Module 6: DDR2 and SCR F3 STATE = 0

    The DDR controller appears to be powered down.  By the way, at what point in time did you actually perform this register dump?  Is this after connecting with JTAG on a failed boot attempt?  Your PLL0 and PLL1 frequencies (i.e. SYSCLK_x) are all ridiculously low.

  • 0 in reply to Brad Griffis
    Prodigy 235 points

    Thanks for the additional tips.  I ended up getting things working by using the starterware bootloader with a minimal AIS configuration.