Original question:
[19:30:32.722]收←◆ResetReg:0x00000000 ROM Checksum Example [19:30:32.759]收←◆Compute ROM-Checksum Data integrity passed TIMER_ESM_init: Init MCU ESM complete Starting MTOG test on MCU MTOG0, index 1... MTOG Status Register Value for the instance1 = 2 Delta MTOG prep time in micro secs 25 Delta MTOG execution time in micro secs 4919 Delta MTOG restore time in micro secs 1 MTOG complete for MCU MTOG0 Sdl mtog instance 1 passed Starting MTOG test on MCU MTOG0, index 2... MTOG Status Register Value for the instance2 = 1 Delta MTOG prep time in micro secs 24 Delta MTOG execution time in micro secs 4912 Delta MTOG restore time in micro secs 1 MTOG complete for MCU MTOG0 Sdl mtog instance 2 passed MTOG Saftey Example passed. TOG Sample Example Init MCU ESM complete SDL_TOG_setIntrEnable complete SDL_TOG_init.timeout complete SDL_TOG_start complete SDL_TOG_stop complete All tests have passed. DCC Example Test Application DCC_Test_init: Init WKUP ESM complete USECASE: 0 Source clock: HFOSC0 Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-0 Completed Successfully USECASE: 1 Source clock: HFOSC0 Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: DCC Generated completion interrupt SDL DCC EXAMPLE TEST: No Clock Drift was observed UC-1 Completed Successfully USECASE: 2 Source clock: HFOSC0 Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and running for some time [19:30:33.329]收←◆UC-2 Completed Successfully USECASE: 3 Source clock: RC OSC Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: DCC Generated completion interrupt SDL DCC EXAMPLE TEST: No Clock Drift was observed UC-3 Completed Successfully USECASE: 4 Source clock: RC OSC Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-4 Completed Successfully USECASE: 5 Source clock: RC OSC Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-5 Completed Successfully USECASE: 6 Source clock: RC OSC Test clock: SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-6 Completed Successfully USECASE: 7 Source clock: HFOSC0 Test clock: MAIN_SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt SDL DCC EXAMPLE TEST: DCC Generated Error interrupt SDL DCC EXAMPLE TEST: Indicating clock drift/change UC-7 Completed Successfully USECASE: 8 Source clock: RC OSC Test clock: MAIN_SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: Enabling DCC and running for some time [19:30:33.907]收←◆UC-8 Completed Successfully USECASE: 9 Source clock: HFOSC0 Test clock: FICLK SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: DCC Generated completion interrupt SDL DCC EXAMPLE TEST: No Clock Drift was observed UC-9 Completed Successfully USECASE: 10 Source clock: FICLK Test clock: MAIN_SYSCLK0 SDL DCC EXAMPLE TEST: Seed values calculation done. SDL DCC EXAMPLE TEST: DCC Generated completion interrupt SDL DCC EXAMPLE TEST: No Clock Drift was observed UC-10 Completed Successfully All tests have passed. Sciclient_pmSetModuleState 0xb6 ...FAILED: retValue -1 Sciclient_pmSetModuleState 0x4b ...FAILED: retValue -1 Sciclient_pmSetModuleState 0xd ...FAILED: retValue -1 Sciclient_pmSetModuleState 0x7 ...FAILED: retValue -1 Sciclient_pmSetModuleState 0x5f ...FAILED: retValue -1 ECC Example Application ECC_Example_init: Init MAIN ESM complete ECC_Example_init: Init WKUP ESM complete ECC_init: AGGR0 ECC Init complete ECC_init: PSRAM ECC Init complete ECC_init: MCU MCAN1 ECC Init complete ESM Safety Example tests: starting MCU MCAN1 Double bit error inject Example test UC-1: starting MCU MCAN1 Double bit error inject test: pError address 0x04E10000 test complete and the value is 0x00000301 Waiting for ESM Interrupt UC-1: Got Low priority ESM Interrupt AGGR0 Single bit error inject Example test UC-2: starting AGGR0 Single bit error inject test: Subtype 0x00000004 test complete Waiting for ESM Interrupt UC-2: Got High priority ESM Interrupt AGGR0 Memory Parity inject Example test UC-3: starting AGGR0 Single bit error self test: Subtype 0x00000001 test complete Waiting for ESM Interrupt UC-3: Memory Parity Error Test Complete PSRAM0 Double bit error inject Example test UC-4: starting PSRAM0 Double bit error inject test: pError address 0x00900000 test complete and the value is 0x00000301 Waiting for ESM Interrupt UC-4: Got Low priority ESM Interrupt ECC Safety Example tests: success ECC UC-1 and UC-2 Test ECC Example passed. Sciclient_pmSetModuleState 0xb6 ...FAILED: retValue -1 Sciclient_pmSetModuleState 0x4b ...FAILED: retValue -1 Sciclient_pmSetModuleState 0xd ...FAILED: retValue -1 Sciclient_pmSetModuleState 0x7 ...FAILED: retValue -1 Sciclient_pmSetModuleState 0x5f ...FAILED: retValue -1 ECC sec test ECC_Test_init: Init MCU ESM complete ECC_Test_init: Init MAIN ESM complete ECC_Test_init: ECC Callback Init complete for MCU ESM ECC_Test_init: ECC Callback Init complete for Main ESM ECC SDL API tests: starting Refer the User Guide for the aggregator information Select the memory to test... ...selected 6 ecc_aggrtest: [6] single bit error self test: SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR starting ECC_Memory_init: [6] SDL_MCU_MSRAM_256K1_MSRAM32KX64E_ECC_AGGR ECC Init complete Self test started accessable RamId 0 starting ecc_aggr_test self test: mainMem 6: accessable mem type test failed, Wrapper type RAM id = 0 Self test started RamId 1 starting Self test started RamId 1 completed Self test started RamId 2 starting Self test started RamId 2 completed ecc_aggr test has failed... Ecc Sec failed. Some SDL selftests failed: g_u16SdlFaultIndex:0x40
I think there is some issue with the way the ECC example is integrated, I will share the code to integrate MSRAM ECC in your application.
Regards,
Nihar Potturu
