AM623: SK-AM62B-P1 PRU DMA Control

Part Number: AM623
Other Parts Discussed in Thread: SK-AM62B-P1

I am working with the SK-AM62B-P1 devkit and attempting to allocate several DMA channels for the UART interfaces using a custom kernel module through the TI k3-udma-glue drivers and pass along the addresses of the allocated ring accelerators to the PRU so it can push host descriptors as needed per transaction. 

 

To support this, I wrote a kernel-module to allocate the DMA channels when a custom device tree node is encountered.  

static int udma_probe(struct platform_device *pdev)
{
    struct device *dev = &pdev->dev;
    struct k3_udma_glue_rx_channel_cfg cfg = {0};
    struct k3_udma_glue_rx_channel *rx_channel;
    int index;
    int error;

    dev_info(dev, "UDMA Hardware Bridge Probing...\n");

    cfg.flow_id_base = 0;
    cfg.flow_id_num = 1;
    cfg.flow_id_use_rxchan_id = false;
    cfg.def_flow_cfg = NULL;
    cfg.remote = false;

    // Request channel from TI glue logic
    rx_channel = k3_udma_glue_request_rx_chn(dev, "uart5_udma_rx", &cfg);
    if (IS_ERR(rx_channel)) 
    {
        dev_err(dev, "Failed to request RX channel (ERR: %pe)\n", rx_channel);
        return PTR_ERR(rx_channel);
    }

    error = k3_udma_glue_enable_rx_chn(rx_channel);
    if(error != 0)
    {
        dev_err(dev, "Failed to enable RX channel (ERR: %d)\n", error);
        return error;
    }

    dev_info(dev, "UDMA Hardware Bridge Probing Finished...\n");    

    return 0;
}

 

custom_dma: custom-dma-controller {
      compatible = “stave,udma-controller”;
      status = “okay”

      dmas = <&main_bcdma 0x4405 0 0>, <&main_bcdma 0xc405 0 0>;
      dmas-names = “uart5_dma_rx”, “uart5_dma_tx”;
};

 

 

When calling k3_udma_glue_enable_rx_chn, I run into the following issues:

  • -EINVAL returned when configuring the dmas node in the device tree based on other samples when taking the form <&main_bcdma 0 0x4405 0>. The k3-udma-glue.c driver expects the PSI-L ID to be first in the list.
  • -EBUSY returned, it appears to be failing a check win k3_dmaring_request_dual_ring when using the fwd_id

 

I also attempted to use the remote flag, but that prevents the glue logic from enabling the channel. My understanding is that enabling the channel requires interactions with the TI SCI, and the PRU does not include a TI SCI interface or at least readily accessible drivers.

 

Is there anything missing in my configuration that would prevent the TI driver from properly allocating the BCDMA RX channel and associated ring buffers?

I followed the steps in 1.2. Building the SDK with Yocto — Processor SDK AM62x Documentation, are there any driver updates or patches that might address this behavior?

 

yocto_build_info.txt 

  • Hello Gavin,

    Apologies for the delayed responses here - I have been out of office for a few weeks, and will continue to be out through the end of August.

    I am passing your thread to a team member familiar with Linux UART, and programming DMA. He also worked on the Linux driver side for this high-speed UART demo which is currently paused in the "rough draft" state. Feel free to ask for the current draft of the driver code if you think it may be interesting for you:
    https://github.com/TexasInstruments/open-pru/tree/a0226750_uart_12mb/examples/uart_12mb 

    I am definitely very interested in enabling your usecase of Linux <--> PRU <--> high speed peripheral interfaces. Please tell us a bit more about how data is flowing in your design, and the anticipated usecases.

    example questions. If you aren't comfortable answering them publicly, please pass the info to Jack and he can feed it back to us privately:

    the UART interfaces are at 3 Mbaud each. What kind of throughput are you expecting? what is the "worst case" high throughput usecase?

    I see both a TX and RX DMA. Where will data be coming from and going to? e.g., will Linux be the one generating and processing data, while PRU just facilitates data transfer between Linux and the UARTs? Will this be purely PRU <--> UART communication? Something else?

    How much data are you planning on sending or receiving in a single message?

    Are there real-time latency requirements in this system? (e.g., data must be on the wire within X timeframe of getting generated; there must be a response on the wire X milliseconds after receiving a UART packet; etc)

    Regards,

    Nick