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AM6442: Some questions about ODT settings

Expert 4716 points

Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG

Hi Champs,

I have few questions about the ODT settings.

Q1. We followed your advice and modified the DDRSS_PHY_65_DATA and DDRSS_PHY_321_DATA from 0x01CC0B01 to 0x07CC0B07.

Which one enables the ODT during idle and write time of the LPDDR4 DQ and DQS lines?

What is the difference between these and the setting in SysConfig ODT settings (for example, DQ ODT and SOC ODT)?

image.png

Q2. When will the SysConfig ODT setting work?

For example, is the DQ ODT only work when the MCU writes the LPDDR4 DRAM?

Then, when the MCU reads data from the DRAM, the DQ ODT will be open load, while the SOC ODT is activated to terminate?

Or are both always working?

 

Regards,

Kien

  •  Your snapshot is showing the settings in section "IO Control B) DRAM IO Configuration" so these are the settings for the DRAM.  Thus the "DQ ODT" setting is for the DQ/DQS ODT during writes.  CA ODT is the termination for the address bus in the DRAM.

    "IO control A) Processor Configuration" section has the termination and drive strength settings for the processor.  Thus this is where you would set the DQ/DQS ODT for reads

    SOC ODT is a setting in the memory that should match ODT Pull-Down DQ/DM setting in IO control A) section.  

    Regards,

    James

  • Hi James, thanks for your answer!

    Meanwhile, I'm also confused with the setting here and the value set in AM64 DDR register DDR16SS_DENALI_PHY_74.

    If I set DQ ODT = 40 ohm here, while I set DDR16SS_DENALI_PHY_74 = 0x01CC0B01. Will the DQ ODT be enabled during the write process?

  • PHY_DQ_TSEL_ENABLE controls the termination on the processor side, so this parameter is always set to 1 so termination will be enabled for reads but disabled for writes.

    Regards,

    James