Part Number: AM6442
Other Parts Discussed in Thread: SYSCONFIG
Hi Champs,
I have few questions about the ODT settings.
Q1. We followed your advice and modified the DDRSS_PHY_65_DATA and DDRSS_PHY_321_DATA from 0x01CC0B01 to 0x07CC0B07.
Which one enables the ODT during idle and write time of the LPDDR4 DQ and DQS lines?
What is the difference between these and the setting in SysConfig ODT settings (for example, DQ ODT and SOC ODT)?

Q2. When will the SysConfig ODT setting work?
For example, is the DQ ODT only work when the MCU writes the LPDDR4 DRAM?
Then, when the MCU reads data from the DRAM, the DQ ODT will be open load, while the SOC ODT is activated to terminate?
Or are both always working?
Regards,
Kien
