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AM6422: What is the maximum supported MDC clock frequency for the MDIO interface?

Daniel Cheng1
Mastermind 8195 points

Part Number: AM6422
Other Parts Discussed in Thread: AM620-Q1

Hi TI Team,

I am working on a custom board design using the AM6422 processor and checking the specifications for the MDC/MDIO interface.

By default, the MDC frequency is configured at 2.5 MHz according to the standard. However, I would like to know the maximum frequency that the AM6422 MDIO controller can legally support and output?

Could you please provide the maximum MDC frequency from the hardware/TRM perspective (e.g., when adjusting the clock divider in the MDIO_CONTROL register)? Also, if there are any specific timing constraints or recommendations when running MDIO at higher speeds, please let me know.

Thank you!

 

Daniel

  • 0
    TI__Genius 13250 points

    Hello Daniel,

    Thank you for reaching out to the TI Sitara MPU Hardware Applications support team.

    Please allow me some time to check and come back with a response in a day or two.

    I appreciate your patience !

    Best Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    Mastermind 8195 points

    Hi Sir

    Could you help this case?

    Thanks

    Daniel

  • 0 in reply to Daniel Cheng1
    TI__Genius 13250 points

    Hi Daniel,

    Sorry for my delayed response !

    The CPSW3g and PRU-ICSS MDIO hardware should allow a maximum MDC frequency as high as 2.5 MHz as per the AM64x Datasheet MDIOs timing characteristics, but according to the AM64x Silicon Revision 1.0,2.0, in the  AM64x SoC SR1.0 (silicon revision) and latest SR2.0, there are hardware limitations over the frequency because of issues described within the: Advisory notes i2329 and i233.

    For more information on these limitations and how to apply the MDIO manual mode workaround to allow MDIO operation, please refer  to the Advisory notes i2329 and i2331 of the AM64x Silicon Revision 1.0,2.0. 

    Here is an excerpt of what is important from the i2329:

    The manual mode MDIO driver with a software bit-banging of the MDC signal shall be used. This means that the clock shall NOT be generated through the MDIO hardware state machine, which shall be disabled, but with a software thread directly toggling the MDC pin in the enabled MDIO manual mode. Therefore the MDC pulse sequence frequency performance  may depend on the CPU workload over time.

    You may want to refer the below thread for more information on how to achieve a sufficient MDIO.MDC clock frequency. Despite, it is regarding AM620-Q1, the described erroneous behavior and workaround are identical: 

    AM620-Q1: Errata i2329, Threads regarding changing MDIO MDC frequency

    AM625: MDC frequency in manual mode

    Please consider also the i2331 advisory workaround - when accessing the  CPSW3g / PRU-ICSS MDIO or other registers right after PORz event. 

    Please let me know if this thread answers your questions ?

    Thanks

    Best Regards,

    Anastas Yordanov