How access input/output buffers in new C6Accel kernels?

Andrea Brandolese

Other Parts Discussed in Thread: DM3730

Hi,

I'm trying to add new kernel function to C6Accel library. I add the source code, the wrapper function and all needed definitions. I compiled it and wirtte the test application. All works fine except the accesing to input (or maybe output) buffers that i pass from test application to C6Accel kernel. My kernel has 1 input buffer and 1 output buffer (unsigned char *) and i want to copy data from inBuf to outBuf. I have allocated the buffers with Memory_CACHED and Memory_CONTIGHEAP options. I use the synchronous process to invoke the kernel.

The result i find in the outBuf is corrupted, only in some parts of the buffer I find the correct data.

Someone had the same problem and have found a solution?

Thanks in advance.

Andrea

over 13 years ago

0 Iain Hunter over 13 years ago

TI__Genius 16130 points

Sounds like a cache management problem as some of the data is correct. What should happen in C6Accel is

Arm - cache wb of input buffer

DSP - cache invalidate on both in and out buffers

DSP - implements algorithm

DSP - cache wb on output buffer

The easiest way to track this is to use CE_DEBUG=2 variable (http://processors.wiki.ti.com/index.php/CE_DEBUG) and then in the log look for the cache API and in particular the sizes of buffers.

0 Andrea Brandolese over 13 years ago in reply to Iain Hunter

Prodigy 30 points

Yes, I thing in a cache management problem too.

For the ARM side there are functions like: Memory_cacheInv(), Memory_cacheWb(), Memory_cacheWbInv.

There are the same or similar functions calling from the DSP side?

0 Iain Hunter over 13 years ago in reply to Andrea Brandolese

TI__Genius 16130 points

C6Accel uses the iUniveral interface of codec engine. Codec Engine handles the cache management internally based on flags.

At the end of C6ACCEL_TI_process() you'll find some lines like these below which control write back

/* report how we accessed the input buffer */
    for (i=0;i<inBufs->numBufs; i++)
     {
        inBufs->descs[i].accessMask = 0;
        XDM_SETACCESSMODE_READ(inBufs->descs[i].accessMask);
      }
    /* and output buffer */
    for (i=0;i< outBufs->numBufs; i++)
     {
        outBufs->descs[i].accessMask = 0;
        XDM_SETACCESSMODE_WRITE(outBufs->descs[i].accessMask);
      }

If you do a CE_DEBUG=2 log you'll get lines like this showing what buffers were handled by cache management - this is on the way into DSP

[DSP] @0,148,222tk: [+0 T:0x87a05344 S:0x87a0905c] OM - Memory_cacheInv> Enter(addr=0x85a0f000, sizeInBytes=300)
[DSP] @0,148,282tk: [+0 T:0x87a05344 S:0x87a0905c] OM - Memory_cacheInv> return
[DSP] @0,148,326tk: [+0 T:0x87a05344 S:0x87a0905c] OM - Memory_cacheInv> Enter(addr=0x867fe000, sizeInBytes=300)
[DSP] @0,148,385tk: [+0 T:0x87a05344 S:0x87a0905c] OM - Memory_cacheInv> return
[DSP] @0,148,431tk: [+0 T:0x87a05344 S:0x87a0905c] OM - Memory_cacheInv> Enter(addr=0x867fc000, sizeInBytes=300)
[DSP] @0,148,490tk: [+0 T:0x87a05344 S:0x87a0905c] OM - Memory_cacheInv> return
[DSP] @0,148,539tk: [+0 T:0x87a05344 S:0x87a0901c] ti.sdo.ce.universal.UNIVERSAL - UNIVERSAL_process> Enter (handle=0x87a04f20, inBufs=0x87a090c4, outBufs=0x87a09188, inOutBufs=0x0, inArgs=0x87e04afc, outArgs=0x87e04b00)

Note this is not from Dm8168/C6A8168 code, but DM3730 and so is showing principles rather than exact text matches.

Processors

Processors forum

How access input/output buffers in new C6Accel kernels?