AM62L: RGB Parallel Display Not Responding

Part Number: AM62L

Hi TI Experts,
I'm trying to interface 24 bit parallel RGB display with a custom AM62L31 board. the dss and drm has been initialised, however there are no visible changes in the display, how can i debug it.

Display Model : KD43G20-40TC-A2 (24 Bit Parallel RGB)
SDK : 12.00.00.07.04

Kernel Dmesg Log:

am62l@tmds62levm:~$ cat /sys/class/drm/card0-DPI-1/status                                                
connected

am62l@tmds62levm:~$ dmesg | grep -iE "drm|dss|panel|fb"
[    0.000000] cma: Reserved 32 MiB at 0x00000000fba00000
[    0.000000] software IO TLB: mapped [mem 0x00000000fb600000-0x00000000fb800000] (2MB)
[    0.286403] /bus@f0000/dss@30200000: Fixed dependency cycle(s) with /panel0
[    0.293734] /panel0: Fixed dependency cycle(s) with /bus@f0000/dss@30200000
[    5.823982] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
[    7.224913] systemd[1]: modprobe@drm.service: Deactivated successfully.
[    7.244325] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
[   16.353066] panel-simple panel0: supply power not found, using dummy regulator
[   16.443105] [drm] Initialized tidss 1.0.0 for 30200000.dss on minor 0
[   16.468022] tidss 30200000.dss: vp0: Clock rate 14062500 differs over 5% from requested 9000000
[   16.529462] tidss 30200000.dss: [drm] fb0: tidssdrmfb frame buffer device
am62l@tmds62levm:~$ modetest
trying to open device '/dev/dri/card0'... done
opened device `TI Keystone DSS` on driver `tidss` (version 1.0.0 at 0)
Encoders:
id      crtc    type    possible crtcs  possible clones
41      40      DPI     0x00000001      0x00000001

Connectors:
id      encoder status          name            size (mm)       modes   encoders
42      41      connected       DPI-1           0x0             1       41
  modes:
        index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
  #0 480x272 56.77 480 488 489 532 272 276 286 298 9000 flags: nhsync, nvsync; type: preferred, driver
  props:
        1 EDID:
                flags: immutable blob
                blobs:

                value:
        2 DPMS:
                flags: enum
                enums: On=0 Standby=1 Suspend=2 Off=3
                value: 0
        5 link-status:
                flags: enum
                enums: Good=0 Bad=1
                value: 0
        6 non-desktop:
                flags: immutable range
                values: 0 1
                value: 0
        4 TILE:
                flags: immutable blob
                blobs:

                value:

CRTCs:
id      fb      pos     size
40      43      (0,0)   (480x272)
  #0 480x272 56.77 480 488 489 532 272 276 286 298 9000 flags: nhsync, nvsync; type: preferred, driver
  props:
        24 VRR_ENABLED:
                flags: range
                values: 0 1
                value: 0
        27 CTM:
                flags: blob
                blobs:

                value:
        28 GAMMA_LUT:
                flags: blob
                blobs:

                value:
        29 GAMMA_LUT_SIZE:
                flags: immutable range
                values: 0 4294967295
                value: 256

Planes:
id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
33      40      43      0,0             0,0     0               0x00000001
  formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15
 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
  props:
        8 type:
                flags: immutable enum
                enums: Overlay=0 Primary=1 Cursor=2
                value: 1
        30 IN_FORMATS:
                flags: immutable blob
                blobs:

                value:
                        01000000000000001d00000018000000
                        01000000900000004152313241423132
                        52413132524731364247313641523135
                        41423135415232344142323452413234
                        42413234524732344247323441523330
                        41423330585231325842313252583132
                        58523135584231355852323458423234
                        52583234425832345852333058423330
                        59555956555956594e56313200000000
                        ffffff1f000000000000000000000000
                        0000000000000000
                in_formats blob decoded:
                         AR12:  LINEAR(0x0)
                         AB12:  LINEAR(0x0)
                         RA12:  LINEAR(0x0)
                         RG16:  LINEAR(0x0)
                         BG16:  LINEAR(0x0)
                         AR15:  LINEAR(0x0)
                         AB15:  LINEAR(0x0)
                         AR24:  LINEAR(0x0)
                         AB24:  LINEAR(0x0)
                         RA24:  LINEAR(0x0)
                         BA24:  LINEAR(0x0)
                         RG24:  LINEAR(0x0)
                         BG24:  LINEAR(0x0)
                         AR30:  LINEAR(0x0)
                         AB30:  LINEAR(0x0)
                         XR12:  LINEAR(0x0)
                         XB12:  LINEAR(0x0)
                         RX12:  LINEAR(0x0)
                         XR15:  LINEAR(0x0)
                         XB15:  LINEAR(0x0)
                         XR24:  LINEAR(0x0)
                         XB24:  LINEAR(0x0)
                         RX24:  LINEAR(0x0)
                         BX24:  LINEAR(0x0)
                         XR30:  LINEAR(0x0)
                         XB30:  LINEAR(0x0)
                         YUYV:  LINEAR(0x0)
                         UYVY:  LINEAR(0x0)
                         NV12:  LINEAR(0x0)
        35 zpos:
                flags: range
                values: 0 0
                value: 0
        36 COLOR_ENCODING:
                flags: enum
                enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                value: 0
        37 COLOR_RANGE:
                flags: enum
                enums: YCbCr limited range=0 YCbCr full range=1
                value: 1
        38 alpha:
                flags: range
                values: 0 65535
                value: 65535
        39 pixel blend mode:
                flags: enum
                enums: Pre-multiplied=0 Coverage=1
                value: 0

Frame buffers:
id      size    pitch

am62l@tmds62levm:~$ 

 

DTS:

\ panel0 {
        compatible = "panel-dpi";
        status = "okay";
        
    bus-format = <0x1017>; 
    bus-flags = <0x6>;
    bpc = <8>;

            port {
                panel_in_rgb: endpoint {                 
                    remote-endpoint = <&dpi_out>;
                };
            };
            panel-timing {          
                   clock-frequency = <9000000>;
                       hactive = <480>;
               vactive = <272>;
               hfront-porch = <8>;
               hback-porch = <43>;
               hsync-len = <1>;
               vback-porch = <12>;
               vfront-porch = <4>;
               vsync-len = <10>;
                       
                       hsync-active = <0>;
               vsync-active = <0>;
               de-active = <1>;
               pixelclk-active = <0>;     
                };
        };
        
&dss {
    status = "okay";
    bootph-all;
    pinctrl-names = "default";
        pinctrl-0 = <&dpi_pins_default>;
};

// remove the below port when dsi is  used (done in overlay). 

&dss_ports {
    /* VP1: DPI Output */        
    port@0 {
        reg = <0>;

        dpi_out: endpoint {
            remote-endpoint = <&panel_in_rgb>;
        };
    };
};

Thanks in advance.

  • Hi Anandhu,
    Can you please try with the panel-simple compatible approach? Reference: AM623: DSS: DPI display on am62x . You'll need to compile the kernel as well, but panel-simple method has been validated by us so easier to provide help with.


    You should not be getting the following error log:

    tidss 30200000.dss: vp0: Clock rate 14062500 differs over 5% from requested 9000000

    P.S Please use code blocks while pasting any code/logs. 

  • Hi Divyansh,

    I have noticed the change in clock freq. after posting the initial query, how can i alter this clock output? the panel requires 5-12MHz. 
    Thanks.

  • Hi Anandhu,
    Can you please try using the panel-simple approach I mentioned in my last post? You can create your own panel node within panel-simple itself or edit existing ones for experiment purposes.

  • Hi Divyansh,

    I have tried the mentioned method, since the panel "newhaven,nhd-4.3-480272ef-atxl" also requires 9MHz, i used same to check it fixes the clock error, but it still shows difference in pixel clock.

    am62l@tmds62levm:~$ dmesg | grep -iE "dss|ddrm|panel|rgb|drm"
    [    0.286192] /bus@f0000/dss@30200000: Fixed dependency cycle(s) with /panel0
    [    0.293522] /panel0: Fixed dependency cycle(s) with /bus@f0000/dss@30200000
    [    5.757321] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
    [    7.140880] systemd[1]: modprobe@drm.service: Deactivated successfully.
    [    7.159129] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
    [   16.166877] panel-simple panel0: supply power not found, using dummy regulator
    [   16.280459] [drm] Initialized tidss 1.0.0 for 30200000.dss on minor 0
    [   16.303256] tidss 30200000.dss: vp0: Clock rate 14062500 differs over 5% from requested 9000000
    [   16.356046] tidss 30200000.dss: [drm] fb0: tidssdrmfb frame buffer device
    am62l@tmds62levm:~$ 
    

    panel0 {
            compatible = "newhaven,nhd-4.3-480272ef-atxl";
            status = "okay";
            /*
    	bus-format = <0x1017>; 
    	bus-flags = <0x6>;
    	bpc = <8>;
    	*/
    
            	port {
             	   panel_in_rgb: endpoint {        	     
             	       remote-endpoint = <&dpi_out>;
             	   };
            	};
            	/*
            	panel-timing {		  
            	       clock-frequency = <9000000>;
                           hactive = <480>;
    		       vactive = <272>;
    		       hfront-porch = <8>;
    		       hback-porch = <43>;
    		       hsync-len = <1>;
    		       vback-porch = <12>;
    		       vfront-porch = <4>;
    		       vsync-len = <10>;
                           
                           hsync-active = <0>;
    		       vsync-active = <0>;
    		       de-active = <1>;
    		       pixelclk-active = <0>;     
           		 };
           		 */
        	};

  • Did you disable the existing HDMI nodes within the DTS?

  • Yes Divyansh, I did. I'll attach the dts file for you to review. From my analysis, the issue is the pixel clock generation. it can't be generated below the specific value mentioned (14062500).

    // SPDX-License-Identifier: GPL-2.0-only or MIT
    /*
     * Device Tree file for the AM62L31 custom board modified from the am62l3 Evaluation Module
     */
    
    /dts-v1/;
    
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/input/input.h>
    #include <dt-bindings/leds/common.h>
    #include <dt-bindings/net/ti-dp83867.h>
    #include <dt-bindings/thermal/thermal.h>
    #include "k3-am62l3.dtsi"
    #include "k3-pinctrl.h"
    
    / {
    	compatible = "ti,am62l3-evm", "ti,am62l3";
    	model = "Texas Instruments AM62L3 Evaluation Module";
    
    	aliases {
    		mmc0 = &sdhci0;
    		mmc1 = &sdhci1;
    	};
    
    	chosen {
    		stdout-path = &uart0;
    	};
    
    	//comment out the below for dual core. 
        	cpus {
        		/delete-node/ cpu@1;
        		/delete-node/ cpu-map;
    
        		cpu-map {
            		cluster0: cluster0 {
                			core0 {
                    			cpu = <&cpu0>;
                			};
           			 };
        		};
    	};
    
    	memory@80000000 {
    		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
    		device_type = "memory";
    		bootph-all;
    	};
    
    
    
    	thermal-zones {
    		wkup0-thermal {
    			polling-delay-passive = <250>;	/* milliSeconds */
    			polling-delay = <500>;		/* milliSeconds */
    			thermal-sensors = <&vtm0 0>;
    
    			trips {
    				crit0 {
    					temperature = <125000>;
    					hysteresis = <2000>;
    					type = "critical";
    				};
    			};
    		};
    	};
    
    	vmain_pd: regulator-0 {
    		/* TPS65988 PD CONTROLLER OUTPUT */
    		compatible = "regulator-fixed";
    		regulator-name = "vmain_pd";
    		regulator-min-microvolt = <5000000>;
    		regulator-max-microvolt = <5000000>;
    		regulator-always-on;
    		regulator-boot-on;
    		bootph-all;
    	};
    
    	vcc_3v3_sys: regulator-1 {
    		/* output of LM61460-Q1 */
    		compatible = "regulator-fixed";
    		regulator-name = "vcc_3v3_sys";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    		vin-supply = <&vmain_pd>;
    		regulator-always-on;
    		regulator-boot-on;
    	};
    
    	vdd_mmc1: regulator-2 {
    		/* TPS22918DBVR */
    		compatible = "regulator-fixed";
    		regulator-name = "vdd_mmc1";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    		regulator-boot-on;
    		enable-active-high;
    		vin-supply = <&vcc_3v3_sys>;
    		
    		bootph-all;
    	};
    
    	vcc_1v8: regulator-3 {
    		/* output of TPS6282518DMQ */
    		compatible = "regulator-fixed";
    		regulator-name = "vcc_1v8";
    		regulator-min-microvolt = <1800000>;
    		regulator-max-microvolt = <1800000>;
    		vin-supply = <&vcc_3v3_sys>;
    		regulator-always-on;
    		regulator-boot-on;
    	};
    
    	tlv320_mclk: clk-0 {
    		#clock-cells = <0>;
    		compatible = "fixed-clock";
    		clock-frequency = <12288000>;
    	};
    	
    	
    	panel0 {
            compatible = "newhaven,nhd-4.3-480272ef-atxl";
            status = "okay";
            /*
    	bus-format = <0x1017>; 
    	bus-flags = <0x6>;
    	bpc = <8>;
    	*/
    
            	port {
             	   panel_in_rgb: endpoint {        	     
             	       remote-endpoint = <&dpi_out>;
             	   };
            	};
            	/*
            	panel-timing {		  
            	       clock-frequency = <9000000>;
                           hactive = <480>;
    		       vactive = <272>;
    		       hfront-porch = <8>;
    		       hback-porch = <43>;
    		       hsync-len = <1>;
    		       vback-porch = <12>;
    		       vfront-porch = <4>;
    		       vsync-len = <10>;
                           
                           hsync-active = <0>;
    		       vsync-active = <0>;
    		       de-active = <1>;
    		       pixelclk-active = <0>;     
           		 };
           		 */
        	};
        	
        	
                   	
    };
    
    &gpio0 {
    	bootph-all;
    };
    
    &i2c0 {
    	pinctrl-names = "default";
    	pinctrl-0 = <&i2c0_pins_default>;
    	clock-frequency = <400000>;
    	status = "okay";
    
    	eeprom@51 {
    		/* AT24C512C-MAHM-T or M24512-DFMC6TG */
    		compatible = "atmel,24c512";
    		reg = <0x51>;
    	};
    };
    
    &i2c3 {
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&i2c3_pins_default>;
        clock-frequency = <400000>;
        
        pcf8563@51 {
            compatible = "nxp,pcf8563";
            reg = <0x51>;
        };
        
    };
    
    &pmx0 {
    	gpio0_ioexp_intr_pins_default: gpio0-ioexp-intr-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x01b0, PIN_INPUT, 7) /* (B12) SPI0_D1.GPIO0_91 */
    		>;
    		bootph-all;
    	};
    
    	i2c0_pins_default: i2c0-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x01cc, PIN_INPUT_PULLUP, 0) /* (B7) I2C0_SCL */
    			AM62LX_IOPAD(0x01d0, PIN_INPUT_PULLUP, 0) /* (A7) I2C0_SDA */
    		>;
    		bootph-all;
    	};
    
    	i2c1_pins_default: i2c1-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x01d4, PIN_INPUT_PULLUP, 0) /* (D7) I2C1_SCL */
    			AM62LX_IOPAD(0x01d8, PIN_INPUT_PULLUP, 0) /* (A6) I2C1_SDA */
    		>;
    		bootph-all;
    	};
    
    	i2c2_pins_default: i2c2-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x01dc, PIN_INPUT_PULLUP, 0) /* (B8) I2C2_SCL */
    			AM62LX_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (D8) I2C2_SDA */
    		>;
    	};
    	
    	i2c3_pins_default: i2c3-default-pins {
                pinctrl-single,pins = <
                        AM62LX_IOPAD(0x01bc, PIN_INPUT|PIN_DRIVE_STRENGTH_NOMINAL, 2) /* (B14) UART0_CTSn.I2C3_SCL */
                        AM62LX_IOPAD(0x01c0, PIN_INPUT|PIN_DRIVE_STRENGTH_NOMINAL, 2) /* (B13) UART0_RTSn.I2C3_SDA */
                >;
            };
    
    	ospi0_pins_default: ospi0-default-pins {
    		bootph-all;
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x003c, PIN_OUTPUT, 0) /* (D22) OSPI0_CLK */
    			AM62LX_IOPAD(0x0068, PIN_OUTPUT, 0) /* (C20) OSPI0_CSn0 */
    			AM62LX_IOPAD(0x0074, PIN_OUTPUT, 0) /* (C23) OSPI0_CSn3 */
    			AM62LX_IOPAD(0x0048, PIN_INPUT, 0) /* (C22) OSPI0_D0 */
    			AM62LX_IOPAD(0x004c, PIN_INPUT, 0) /* (D21) OSPI0_D1 */
    			AM62LX_IOPAD(0x0050, PIN_INPUT, 0) /* (E23) OSPI0_D2 */
    			AM62LX_IOPAD(0x0054, PIN_INPUT, 0) /* (D23) OSPI0_D3 */
    			AM62LX_IOPAD(0x0058, PIN_INPUT, 0) /* (F21) OSPI0_D4 */
    			AM62LX_IOPAD(0x005c, PIN_INPUT, 0) /* (F19) OSPI0_D5 */
    			AM62LX_IOPAD(0x0060, PIN_INPUT, 0) /* (G20) OSPI0_D6 */
    			AM62LX_IOPAD(0x0064, PIN_INPUT, 0) /* (F20) OSPI0_D7 */
    			AM62LX_IOPAD(0x0044, PIN_INPUT, 0) /* (E22) OSPI0_DQS */
    			AM62LX_IOPAD(0x0040, PIN_INPUT, 0) /* (E18) OSPI0_LBCLKO */
    		>;
    	};
    
    	mmc0_pins_default: mmc0-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x0214, PIN_INPUT, 0) /* (D2) MMC0_CMD */
    			AM62LX_IOPAD(0x020c, PIN_OUTPUT, 0) /* (B2) MMC0_CLK */
    			AM62LX_IOPAD(0x0208, PIN_INPUT, 0) /* (D3) MMC0_DAT0 */
    			AM62LX_IOPAD(0x0204, PIN_INPUT_PULLUP, 0) /* (D4) MMC0_DAT1 */
    			AM62LX_IOPAD(0x0200, PIN_INPUT_PULLUP, 0) /* (C1) MMC0_DAT2 */
    			AM62LX_IOPAD(0x01fc, PIN_INPUT_PULLUP, 0) /* (C2) MMC0_DAT3 */
    			AM62LX_IOPAD(0x01f8, PIN_INPUT_PULLUP, 0) /* (C4) MMC0_DAT4 */
    			AM62LX_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (B3) MMC0_DAT5 */
    			AM62LX_IOPAD(0x01f0, PIN_INPUT_PULLUP, 0) /* (A3) MMC0_DAT6 */
    			AM62LX_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (B4) MMC0_DAT7 */
    		>;
    		bootph-all;
    	};
    
    	mmc1_pins_default: mmc1-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x0230, PIN_INPUT, 0) /* (Y3) MMC1_CMD */
    			AM62LX_IOPAD(0x0228, PIN_OUTPUT, 0) /* (Y2) MMC1_CLK */
    			AM62LX_IOPAD(0x0224, PIN_INPUT, 0) /* (AA1) MMC1_DAT0 */
    			AM62LX_IOPAD(0x0220, PIN_INPUT, 0) /* (Y4) MMC1_DAT1 */
    			AM62LX_IOPAD(0x021c, PIN_INPUT, 0) /* (AA2) MMC1_DAT2 */
    			AM62LX_IOPAD(0x0218, PIN_INPUT, 0) /* (AB2) MMC1_DAT3 */
    			AM62LX_IOPAD(0x0234, PIN_INPUT, 0) /* (B6) MMC1_SDCD */
    		>;
    		bootph-all;
    	};
    
    	dpi_pins_default: dpi-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x00e4, PIN_OUTPUT, 1) /* (L20) GPMC0_CSn0.VOUT0_VSYNC */
    			AM62LX_IOPAD(0x00dc, PIN_OUTPUT, 1) /* (N21) GPMC0_WPn.VOUT0_HSYNC */
    			AM62LX_IOPAD(0x00e8, PIN_OUTPUT, 1) /* (L19) GPMC0_CSn1.VOUT0_PCLK */
    			AM62LX_IOPAD(0x00e0, PIN_OUTPUT, 1) /* (M21) GPMC0_DIR.VOUT0_DE */
    			AM62LX_IOPAD(0x0078, PIN_OUTPUT, 1) /* (L22) GPMC0_AD0.VOUT0_DATA0 */
    			AM62LX_IOPAD(0x007c, PIN_OUTPUT, 1) /* (L23) GPMC0_AD1.VOUT0_DATA1 */
    			AM62LX_IOPAD(0x0080, PIN_OUTPUT, 1) /* (K22) GPMC0_AD2.VOUT0_DATA2 */
    			AM62LX_IOPAD(0x0084, PIN_OUTPUT, 1) /* (J23) GPMC0_AD3.VOUT0_DATA3 */
    			AM62LX_IOPAD(0x0088, PIN_OUTPUT, 1) /* (K23) GPMC0_AD4.VOUT0_DATA4 */
    			AM62LX_IOPAD(0x008c, PIN_OUTPUT, 1) /* (H22) GPMC0_AD5.VOUT0_DATA5 */
    			AM62LX_IOPAD(0x0090, PIN_OUTPUT, 1) /* (H23) GPMC0_AD6.VOUT0_DATA6 */
    			AM62LX_IOPAD(0x0094, PIN_OUTPUT, 1) /* (J22) GPMC0_AD7.VOUT0_DATA7 */
    			AM62LX_IOPAD(0x0098, PIN_OUTPUT, 1) /* (H19) GPMC0_AD8.VOUT0_DATA8 */
    			AM62LX_IOPAD(0x009c, PIN_OUTPUT, 1) /* (H20) GPMC0_AD9.VOUT0_DATA9 */
    			AM62LX_IOPAD(0x00a0, PIN_OUTPUT, 1) /* (H21) GPMC0_AD10.VOUT0_DATA10 */
    			AM62LX_IOPAD(0x00a4, PIN_OUTPUT, 1) /* (H18) GPMC0_AD11.VOUT0_DATA11 */
    			AM62LX_IOPAD(0x00a8, PIN_OUTPUT, 1) /* (G23) GPMC0_AD12.VOUT0_DATA12 */
    			AM62LX_IOPAD(0x00ac, PIN_OUTPUT, 1) /* (G22) GPMC0_AD13.VOUT0_DATA13 */
    			AM62LX_IOPAD(0x00b0, PIN_OUTPUT, 1) /* (F22) GPMC0_AD14.VOUT0_DATA14 */
    			AM62LX_IOPAD(0x00b4, PIN_OUTPUT, 1) /* (F23) GPMC0_AD15.VOUT0_DATA15 */
    			AM62LX_IOPAD(0x00b8, PIN_OUTPUT, 1) /* (L21) GPMC0_CLK.VOUT0_DATA16 */
    			AM62LX_IOPAD(0x00c0, PIN_OUTPUT, 1) /* (N19) GPMC0_ADVn_ALE.VOUT0_DATA17 */
    			AM62LX_IOPAD(0x00c4, PIN_OUTPUT, 1) /* (N20) GPMC0_OEn_REn.VOUT0_DATA18 */
    			AM62LX_IOPAD(0x00c8, PIN_OUTPUT, 1) /* (M19) GPMC0_WEn.VOUT0_DATA19 */
    			AM62LX_IOPAD(0x00cc, PIN_OUTPUT, 1) /* (P23) GPMC0_BE0n_CLE.VOUT0_DATA20 */
    			AM62LX_IOPAD(0x00d0, PIN_OUTPUT, 1) /* (P22) GPMC0_BE1n.VOUT0_DATA21 */
    			AM62LX_IOPAD(0x00d4, PIN_OUTPUT, 1) /* (N23) GPMC0_WAIT0.VOUT0_DATA22 */
    			AM62LX_IOPAD(0x00d8, PIN_OUTPUT, 1) /* (N22) GPMC0_WAIT1.VOUT0_DATA23 */
    			AM62LX_IOPAD(0x00ec, PIN_OUTPUT, 5) /* (M23) GPMC0_CSn2.VOUT0_EXTPCLKIN */
    		>;
    		bootph-all;
    	};
    
    	rgmii1_pins_default: rgmii1-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x0138, PIN_INPUT, 0) /* (Y8) RGMII1_RD0 */
    			AM62LX_IOPAD(0x013c, PIN_INPUT, 0) /* (AA6) RGMII1_RD1 */
    			AM62LX_IOPAD(0x0140, PIN_INPUT, 0) /* (AA8) RGMII1_RD2 */
    			AM62LX_IOPAD(0x0144, PIN_INPUT, 0) /* (W8) RGMII1_RD3 */
    			AM62LX_IOPAD(0x0134, PIN_INPUT, 0) /* (Y7) RGMII1_RXC */
    			AM62LX_IOPAD(0x0130, PIN_INPUT, 0) /* (Y6) RGMII1_RX_CTL */
    			AM62LX_IOPAD(0x0120, PIN_OUTPUT, 0) /* (AC10) RGMII1_TD0 */
    			AM62LX_IOPAD(0x0124, PIN_OUTPUT, 0) /* (W13) RGMII1_TD1 */
    			AM62LX_IOPAD(0x0128, PIN_OUTPUT, 0) /* (Y11) RGMII1_TD2 */
    			AM62LX_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AA11) RGMII1_TD3 */
    			AM62LX_IOPAD(0x011c, PIN_OUTPUT, 0) /* (W11) RGMII1_TXC */
    			AM62LX_IOPAD(0x0118, PIN_OUTPUT, 0) /* (AB11) RGMII1_TX_CTL */
    		>;
    	};
    
    	rgmii2_pins_default: rgmii2-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x0170, PIN_INPUT, 0) /* (AB9) RGMII2_RD0 */
    			AM62LX_IOPAD(0x0174, PIN_INPUT, 0) /* (AC9) RGMII2_RD1 */
    			AM62LX_IOPAD(0x0178, PIN_INPUT, 0) /* (AB10) RGMII2_RD2 */
    			AM62LX_IOPAD(0x017c, PIN_INPUT, 0) /* (AB8) RGMII2_RD3 */
    			AM62LX_IOPAD(0x016c, PIN_INPUT, 0) /* (AC7) RGMII2_RXC */
    			AM62LX_IOPAD(0x0168, PIN_INPUT, 0) /* (AC8) RGMII2_RX_CTL */
    			AM62LX_IOPAD(0x0158, PIN_OUTPUT, 0) /* (AC12) RGMII2_TD0 */
    			AM62LX_IOPAD(0x015c, PIN_OUTPUT, 0) /* (AB13) RGMII2_TD1 */
    			AM62LX_IOPAD(0x0160, PIN_OUTPUT, 0) /* (AA12) RGMII2_TD2 */
    			AM62LX_IOPAD(0x0164, PIN_OUTPUT, 0) /* (AA13) RGMII2_TD3 */
    			AM62LX_IOPAD(0x0154, PIN_OUTPUT, 0) /* (Y13) RGMII2_TXC */
    			AM62LX_IOPAD(0x0150, PIN_OUTPUT, 0) /* (AB12) RGMII2_TX_CTL */
    		>;
    	};
    
    	mdio1_pins_default: mdio1-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x014c, PIN_OUTPUT, 0) /* (AC15) MDIO0_MDC */
    			AM62LX_IOPAD(0x0148, PIN_INPUT, 0) /* (AC13) MDIO0_MDIO */
    		>;
    	};
    
    	uart0_pins_default: uart0-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x01b4, PIN_INPUT, 0) /* (D13) UART0_RXD */
    			AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */
    		>;
    		bootph-all;
    	};
    
    	uart0_pins_wakeup: uart0-wakeup-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x01b4, PIN_INPUT | PIN_WKUP_EN, 0) /* (D13) UART0_RXD */
    			AM62LX_IOPAD(0x01b8, PIN_OUTPUT, 0) /* (C13) UART0_TXD */
    		>;
    	};
    
    	usb1_default_pins: usb1-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x0248, PIN_INPUT | PIN_DS_PULLUD_ENABLE | PIN_DS_PULL_UP, 0) /* (A5) USB1_DRVVBUS */
    		>;
    	};
    
    	main_mcasp0_pins_default: main-mcasp0-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x0190, PIN_INPUT, 0) /* (A11) MCASP0_ACLKX */
    			AM62LX_IOPAD(0x0194, PIN_INPUT, 0) /* (B11) MCASP0_AFSX */
    			AM62LX_IOPAD(0x018c, PIN_INPUT, 0) /* (B9) MCASP0_AXR0 */
    			AM62LX_IOPAD(0x0188, PIN_INPUT, 0) /* (A9) MCASP0_AXR1 */
    		>;
    	};
    
    	usr_button_pins_default: usr-button-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x01ac, PIN_INPUT, 7) /* (E12) SPI0_D0.GPIO0_90 */
    		>;
    	};
    
    	usr_led_pins_default: usr-led-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x0238, PIN_OUTPUT, 7) /* (D24) MMC1_SDWP.GPIO0_123 */
    		>;
    	};
    
    	wkup_uart0_pins_default: wkup-uart0-default-pins {
    		pinctrl-single,pins = <
    			AM62LX_IOPAD(0x0000, PIN_INPUT, 0) /* (Y22) WKUP_UART0_RXD */
    			AM62LX_IOPAD(0x0004, PIN_OUTPUT, 0) /* (AA23) WKUP_UART0_TXD */
    		>;
    	};
    };
    
    &sdhci0 {
    	/* eMMC */
    	pinctrl-names = "default";
    	pinctrl-0 = <&mmc0_pins_default>;
    	non-removable;
    	status = "okay";
    	bootph-all;
    };
    
    &sdhci1 {
    	/* SD/MMC */
    	pinctrl-names = "default";
    	pinctrl-0 = <&mmc1_pins_default>;
    	vmmc-supply = <&vdd_mmc1>;
    	/delete-property/ ti,otap-del-sel-sdr12;
        /delete-property/ ti,otap-del-sel-sdr25;
        /delete-property/ ti,otap-del-sel-sdr50;
        /delete-property/ ti,otap-del-sel-ddr50;
        /delete-property/ ti,otap-del-sel-sdr104;
        no-1-8-v;
    	disable-wp;
    	status = "okay";
    	bootph-all;
    };
    
    
    &cpsw_port1 {
    	phy-mode = "rgmii-rxid";
    	phy-handle = <&cpsw3g_phy0>;
    };
    
    &cpsw_port2 {
    	phy-mode = "rgmii-rxid";
    	phy-handle = <&cpsw3g_phy1>;
    };
    
    &cpsw3g_mdio {
    	pinctrl-names = "default";
    	pinctrl-0 = <&mdio1_pins_default>;
    	status = "okay";
    
    	cpsw3g_phy0: ethernet-phy@7 {
    		reg = <7>;
    		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
    		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
    		ti,min-output-impedance;
    	};
    
    	cpsw3g_phy1: ethernet-phy@1 {
    		reg = <1>;
    		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
    		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
    		ti,min-output-impedance;
    	};
    };
    
    &uart0 {
    	pinctrl-0 = <&uart0_pins_default>;
    	pinctrl-1 = <&uart0_pins_wakeup>;
    	pinctrl-names = "default", "wakeup";
    	wakeup-source;
    	status = "okay";
    	bootph-all;
    };
    
    &usbss1 {
    	status = "okay";
    	ti,vbus-divider;
    };
    
    &usb1 {
    	dr_mode = "host";
    	pinctrl-names = "default";
    	pinctrl-0 = <&usb1_default_pins>;
    };
    
    
    
    &main_bcdma {
    	bootph-all;
    };
    
    &main_pktdma {
    	bootph-all;
    };
    
    &dss {
    	status = "okay";
    	bootph-all;
    	pinctrl-names = "default";
        	pinctrl-0 = <&dpi_pins_default>;
    };
    
    // remove the below port when dsi is  used (done in overlay). 
    
    &dss_ports {
        /* VP1: DPI Output */        
        port@0 {
            reg = <0>;
    
            dpi_out: endpoint {
                remote-endpoint = <&panel_in_rgb>;
            };
        };
    };
    
    &wkup_uart0 {
    	pinctrl-0 = <&wkup_uart0_pins_default>;
    	pinctrl-names = "default";
    };
    
    &wkup_uart0_interconnect {
    	status = "okay";
    };
    
    &mcasp0 {
    	status = "okay";
    	#sound-dai-cells = <0>;
    
    	pinctrl-names = "default";
    	pinctrl-0 = <&main_mcasp0_pins_default>;
    
    	op-mode = <0>;			/* MCASP_IIS_MODE */
    	tdm-slots = <2>;
    
    	serial-dir = <  /* 0: INACTIVE, 1: TX, 2: RX */
    	       1 2 0 0
    	       0 0 0 0
    	       0 0 0 0
    	       0 0 0 0
    	>;
    };

  • Okay, allow me some time to reproduce this at my end. Will get back by mid next week.

  • Could you please mention the min and max pixel clock frequencies the dss is able to generate?. 

    I noticed two conflicting pixel clock frequency specs in the AM62L TRM:

    1. Section 12.7.2.6.2 (DPI Pixel Stream Interface) states: pixel clock range 7 MHz – 425 MHz
    2. Table 12-351 (DSS Signals for MIPI DPI 2.0 / BT.656/BT.1120) states: DPI0_PCLK maximum interface frequency is 165 MHz

    Which is the correct maximum and minimum pixel clock frequency for DPI0_PCLK on the AM62L?

  • It is 7MHz to 165 MHz.

  • Hi Anandhu,
    I have been able to replicate the issue at my end and have filed a bug for our dev team to look at. Will post the fix here as and when we have it.
    7MHz is the min expected for the software to allow (but may as well be able to go to 6.25MHz (cannot promise on this)). Will keep you updated.

  • Hi Divyansh,

    I'll wait for the reply. Thank you.

  • Hi Anandhu,
    Thanks for waiting.
    The following patch file can be used in the ti-processor-sdk-linux-am62lxx-evm-12.00.00.07.04/board-support/trusted-firmware-a-2.14+git repo:

    diff --git a/drivers/ti/clk/ti_clk_div.c b/drivers/ti/clk/ti_clk_div.c
    index cc539bb8f..de6415c03 100644
    --- a/drivers/ti/clk/ti_clk_div.c
    +++ b/drivers/ti/clk/ti_clk_div.c
    @@ -327,7 +327,7 @@ uint32_t ti_clk_div_set_freq_static_parent(struct ti_clk *clkp, uint32_t target_
     	div1_hz = 0U;
     	if (div1 <= n) {
     		div1_hz = parent_freq_hz / div1;
    -		if (div1_hz >= min_hz) {
    +		if ((div1_hz >= min_hz) && (div1_hz <= max_hz)) {
     			div1_ok = true;
     			div1_delta = target_hz - div1_hz;
     		} else {
    

    Note, the makefile to build atf is already there in the makerules folder. You may also refer to this if needed: https://software-dl.ti.com/processor-sdk-linux/esd/AM62LX/latest/exports/docs/linux/Foundational_Components_ATF.html 

    This fix will come into SDK a little late (SDK release 12.02) hence provided you the patch here.

  • Hi Divyansh,

    I couldn't find ti_clk_div.c in that directory, so I applied the changes to plat/ti/k3/common/drivers/pm/clock/clk_div.c. It looks like the frequency warning has disappeared.

    Regards.

  • Hi Anandhu,
    The path you mentioned is applicable on 11.02 SDK, while one I gave is for 12.0. Anyhow, glad your issue is resolved.