We're using a AM398x evaluation board and using ARM mode. The Cortex-A8 core should in theory be an ARM v7 implementation, and according to the ARM v7 Architecture Reference manual (ARM DDI 0406C), section A 3.2.1 'Unaligned data access':
"An ARMv7 implementation must support unaligned data accesses by some load and store instructions, as Table A3-1 shows. Software can set the SCTLR.A bit to control whether a misaligned access by one of these instructions causes an Alignment fault Data Abort exception"
In table A3-1, it shows that LDRH, for example, in principle requires a half word alignment. But on an alignment check failure, behavior should be either an alignment fault (if SCTLR.A = 1), or an unaligned access (if SCTLR.A = 0)
However, I still get a data abort with any setting on SCTLR.A when trying to load a half word from an odd address as shown in the snippet below. Is this hardware support for unaligned data access not implemented in the chip or am I missing something?
MOVW R8, 0x2a57
MOVT R8, 0x8005
LDRH R0,[R8]
Thanks!
