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Other Parts Discussed in Thread: OMAP-L138Hey everybody,
I’ve got an issue with the GOSTAT[0] bit in the PDSTAT register of PSC0 is spontaneously setting to a ‘1’.
The board I’m working on has two OMAP-L138’s setup in a Master/Slave arrangement with a FPGA acting as a FIFO between them.
Both OMAP’s are configured to boot from SPI flash.
I have hacked the AIS/UBL boot loader source code to insert a check -before- DEVICE_Init().
The code I added to the UBL implements some loop counters which see the GOSTAT[0] bit being zero for a period of time and then
sees the GOSTAT[0] bit flip to a ‘1’. This indicates that ‘Power Domain 0 or modules in the power domain are in transition’.
The weird part is that the source code has not commanded any power/state transitions yet.
If I ignore this stuck GOSTAT[0] bit then I can boot u-boot and the Linux kernel by hacking out their checks of GOSTAT[0].
The Master OMAP-L138 processor on the same card does not exhibit this behavior – only the slave which is held in reset until the FPGA is loaded.
Does anybody know what –exactly- that GOSTAT[0] bit is detecting?
Cheers
Jeff