All,
I'm working on hooking up an AM3517 to 3 separate, but identical, audio chips (voice quality only) using 3 McBSP interfaces. For our implementation, only McBSPs 2, 3, and 4 are available. So, 4-wire interfaces only (no McBSP1).
The audio chip we need to use is a 4-wire interface only, and only supports master mode. It must source both the CLK and FS lines to the McBSP. We assumed this would be fairly trivial since the TRM says the McBSP can be put into slave mode, however we've hit a few snags.
We have our transmit side working decently. Audio is passing, and aside from momentary glitches it sounds pretty good. We're presuming we just have some minor settings to tune, buffers, irqs, etc.
We are getting nothing on the receive path but silence, however. As we have poured back through the TI documentation (sprf98u.pdf), we've found ourselves getting more and more confused. Can you please help us sort this out?
To start with, here are our present register settings. (Please let us know if you need to see something else.)
regs->rcr2 = 0x00000040
regs->xcr2 = 0x00000040
regs->rcr1 = 0x00000040
regs->xcr1 = 0x00000040
regs->srgr2 = 0x0000201f
regs->srgr1 = 0x00000f00
regs->spcr1 = 0x00004030
regs->pcr0 = 0x00000080
regs->xccr = 0x00001009
regs->rccr = 0x00000809
Out of that, the relevant bits for now I think are:
CLKSM=1
SCLKME=1
FSXM=0
FSRM=0
CLKXM=0
CLKRM=0
Section 18.3.2.2.2 (page 1998) says, “Only, the CLKX signal is connected by mcbsp2_clkx pads. The CLKR signal is connected to the CLKX signal. These signals are used like functional clocks by the intermediary of the SRG.” So, that leads me to believe if I get CLKX right, CLKR will follow. However, Figure 18-21 (page 2012) shows “FSR” and “CLKR” as circled in red with a note “McBSP1 only” pointing to them. Figure 18-22 (on the next page, 2013) shows a CLKR for McBSP2, but not how it's attached. And, nothing like that is said about the frame sync pulses. Here is a more detailed breakdown.
*CLKSM & SCLKME:
We want our clock derived from external McBSPi_CLKX pin for each McBSP. (We cannot use the common CLKS pin since we're looking at multiple, independent audio chips each sourcing their own clock.)
Table 18-25 on page 2053 says to set CLKSM=1 and SCLKME=1 to use the “mcbsp_clkx pin” - which we are assuming is the same as the “mcbspI_clkx” pin. (Is this true?)
*CLKX_int:
Section 18.4.2.3.1 (page 2016) says, CLKXM=0 sets CLKX_int to use mcbspi_clkx as input. (CLKXM=1 would make mcbspi_clkx an output; not possible for us.) CLKX_int = mcbspi_clkx (CLKX) pin. That's what we want.
*FSX_int:
Section 18.4.2.3.3 (page 2018) says, FSXM=0 sets FSX_int to use mcbspi_fsx as input. (CLKXM=1 would make mcbspi_fsx an output; not possible for us.) FSX_int = mcbspi_fsx (FSX) pin. That's what we want.
NOW FOR THE INTERESTING ONES...
*CLKR_int:
Table 18-15 (page 2017) shows that for CLKRM=0 & DLB=0, “CLKR_int is driven by an external clock”.
Which clock??? We have no external receive clock pin on McBSP[2-4], and cannot set CLKRM=1 or that's an output.
*FSR_int:
Section 18.4.2.3.3 (page 2018) says, FSRM=0 means, “FSR_int is generated by an external source and mcbspi_fsr is an input pin” However, McBSP2 does NOT have an mcbspi_fsr pin.
The other option, FSRM=1, means, “FSR_int is generated internally by sample rate generator. The mcbspi_fsx is an output pin except when McBSPi.MCBSPLP_SRGR2_REG[15] GSYNC bit = 0x1”. That's definitely NOT what we want either.
So, how can we simply set FSR_int to use the same frame sync pulse as FSX???
So all we really want is all the frame-syncs coming from the one external frame sync pin,mcbspi_fsx, and all the clocks coming from the one external clock pin, mcbspi_clkx.
Getting there is presently stumping us. Perhaps we're reading too much into the documentation, but at the moment we're stumped as to how to properly set this up. We are using a current version of Linux. So, there could be some issues there as well. However, we know that if we don't get the registers setup right, nothing else will matter.
Thanks!
