• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 482 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

question about DDR3 SDRAM PCB layout and routing

yuqing cai
Intellectual 740 points

Hi, every one :~)

We are using DDR3 SDRAM on our DM8168 hardware platform, I have some question about the DDR3 PCB layout and routing rules.
As the DM8168 EVM, we are using 8 DDR3 chips(4 chips per bank). We know that the signals in one DDR3 chip is separated into 4 groups(Data/Data strobe, Address, Command/Control, Clock).  Is it necessary to control the signal length matching between the different DDR3 chips? If so, how to control it?


Best Regards

qing