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TDA4VM: serdes 1 clock setting failing when we do warm reset its sporadic issue

manoj goud
Prodigy 20 points

Part Number: TDA4VM

Doing the following test.

  1. doing warm reset
  2. serdes1 clock setting failing sporadically.

out of 1000 warm resets sporadically failing 10 times.

 

code:


// Enable SERDES 10G1
if (ti_sci_set_device_state(TISCI_DEV_SERDES_10G1, 0, MSG_DEVICE_SW_STATE_ON) == -1) {
kprintf("%s: Set SERDES10G1 device state failed!\n", __func__);
return -1;
}

// Use 156.25Mhz clock for SERDES1
if (ti_sci_cmd_set_clk_parent(TISCI_DEV_SERDES_10G1, TISCI_DEV_SERDES_10G1_CORE_REF_CLK,
TISCI_DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK) == -1) {
kprintf("%s: Set SERDES10G1 Ref clock parent failed!\n", __func__);
return -1;
}

// Set 156.25Mhz reference clock
if (ti_sci_cmd_clk_set_freq(TISCI_DEV_SERDES_10G1, TISCI_DEV_SERDES_10G1_CORE_REF_CLK,
156250000ULL, 156250000ULL, 156250000ULL) == -1) {
kprintf("%s: Set SERDES10G1 RCLK frequency failed!\n", __func__);
return -1;
}
 
issue log:
 
Issue MAPC/SYNC/INVALL commands for ICID 0
update CWRITER to 0x00000060
Waiting for all commands to be processed ... Done in 1 tries
Enable LPIs in GICR_CTLR @ 0000000001900000 for CPU0
ti_sci_recv_message, unable to receive message
init_gpu: Set GPU device (182) state failed!

ti_sci_recv_message, unable to receive message
init_cpsw9g: Set SERDES10G1 Ref clock parent failed!
can you please guide why it is failing.
 
As per the above flow, A72 requesting the DMSC to set the clock frequency. But DMSC denying.
 
please let me know.
  • 0
    TI__Guru* 79470 points

    Hi,


    Could you please check whether SerDes1 is enabled from any other core before Linux configures?

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    Hi Sudheer,

    In A72 core only qnx configures Serdes 1 clock.

    serveral warm reset it works correctly. Only some warm resets clock configuration failed.

    Out 1000/10 times its failed.

  • 0 in reply to manoj goud
    TI__Guru* 79470 points

    Hi,

    The failure of clock set can happen only when it is already being configured by any other core.

    If the request is timeout, then it could due to DM serving other requests.

    Additionally can you confirm in issue scenario is DM core running? Can you check any Sciclient request is success or not post failure of clock setting?

    Best Regards,
    Sudheer

  • 0 in reply to Doredla Sudheer Kumar
    Prodigy 20 points

    hi,

    static int ti_sci_do_xfer(const void *const tbuf, const int tsize, void *const rbuf, const int rsize)
    {
    if (ti_sci_send_message(tbuf, tsize) != 0) {
    return (-1);
    }

    if (ti_sci_recv_message(rbuf, rsize) != 0) {
    return (-1);
    }

    return (0);
    }
    Send message was sucess, only receive message was failure.
    plesae see in logs also.
    ti_sci_recv_message, unable to receive message
    init_cpsw9g: Set SERDES10G1 Ref clock parent failed!
    Hope its not a timeout issue. Because before timeout failure log,ti_sci_do_xfer function called.
    Additionally can you confirm in issue scenario is DM core running? -- will check and inform to you.
  • 0 in reply to manoj goud
    TI__Guru* 79470 points

    Hi, 

    Usually all Sciclient requests are timeout or wait for ever requests. 

    Request might be sent from A72, if DM(MCU1_0) is not running request message won't be serviced. 

    manoj goud said:
    Additionally can you confirm in issue scenario is DM core running? -- will check and inform to you

    could you please confirm this? 

    Best Regards, 

    Sudheer