SRIO between C6678 and FPGA

haopeng han

I am testing the SRIO between TMX320C6678 and FPGA (EP4SGX180). Every time the DSP begins initialize the link--

 /*Set BOOT_COMPLETE bit*/
    srioRegs->RIO_PER_SET_CNTL |= (1 << CSL_SRIO_RIO_PER_SET_CNTL_BOOT_COMPLETE_SHIFT);

the "port_initialized" indicator in FPGA begins to flash while it should be '1'. Port status in DSP seems OK.

Has someone done this kind of test before ? Any idea?

Thanks!

Han

over 13 years ago

0 Chad Courtney over 13 years ago

TI__Mastermind 30825 points

We've done link testing w/ other DSPs, FPGA's and SRIO Switches, but I'm not aware of specific testing with this FPGA. It sounds like the FPGA may be having issues getting a link. Have you contacted the FPGA vendor?

Best Regards,

Chad

0 tscheck over 13 years ago

TI__Mastermind 23525 points

Boot_complete is the last bit to be set during initialization of the peripheral. Once it is set, it kicks off the SRIO link initialization/sync process with the link partner. Before that, only garbage is sent on the link. You should not see port_ok on the DSP side, but not on the FPGA side. They should go high almost simultaneously. Can you confirm that? Also, how are you connecting the devices? Is this on a custom board of yours?

Regards,

Travis

0 haopeng han over 13 years ago in reply to tscheck

Expert 1120 points

Thank you guys for the reply!

I am about to consult Altera on this issue.

After setting Boot_complete, DSP passes port check:

    srioRegs->RIO_PCR|= CSL_SRIO_RIO_PCR_PEREN_MASK;

	/*---------wait all enabled ports OK-------------*/
	for(i=0; i<SRIO_MAX_PORT_NUM; i++)
	{
		if(srio_cfg->blockEn.bLogic_Port_EN[i])
		{
			while(0==(srioRegs->RIO_SP[i].RIO_SP_ERR_STAT&
				CSL_SRIO_RIO_SP_ERR_STAT_PORT_OK_MASK));
		}
	}

However right after Boot_complete is set, the "port_initialized" indicator in FPGA seems in a random state.

The two devices are both on our custom board. The SRIO links are AC couple 100Ohm controlled.

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SRIO between C6678 and FPGA