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TMS320C6657: EMIF and sysclkout relationship

Luca Montini
Prodigy 10 points

Part Number: TMS320C6657

I need to interface TMS320C6657 EMIF with a Block Dual Port in ARTIX7 FPGA. I would like to maximize the speed and I was thinking about using SYSclkout to clock the Dual port inside FPGA. Is it possible ? wich is the timing relationship between SYSclkout and EMIF signals? 

If it is not possible to use sysclkout which is the fastest way to interface EMIF with the dual port avoiding metastability?

  • 0
    TI__Expert 7090 points

    Hi Luca,

    Let me check this and get back to you.

    Regards,

    Betsy Varughese

  • 0
    TI__Intellectual 2840 points

    Hi Luca,

    Luca Montini said:
    I would like to maximize the speed and I was thinking about using SYSclkout to clock the Dual port inside FPGA. Is it possible ? wich is the timing relationship between SYSclkout and EMIF signals? 

    SYSCLKOUT comes from SYSCLK7 (core ÷ 6, the same clock as EMIF16), but TI doesn't specify the timing between the SYSCLKOUT pin and the EMIF16 pins, it's only a debug output, and the EMIF16 signals are asynchronous with ±3 ns of edge uncertainty. So there's no guaranteed margin to design against.

    Instead, could you try capturing on the EMIF strobes at your end? Since address/data timing is specified relative to OE/WE/CE, latch write data into Port A on the EMIFWE edge, and run Port B on your own FPGA clock, the Block Dual-Port RAM then handles the clock-domain crossing itself, so there's no metastability on the data path (just keep the DSP and FPGA in separate address regions). On reads, if your BRAM can't meet the DSP's 3 ns setup, use EM_WAIT to stall until data is ready.

    Regards,
    Shabary S Sundar