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Original question:

TDA4VM: TDA4VM - Heterogenous development

TDA4VM: TDA4VM - Pinmux issue in Uboot SPL

Prasanna Raghunathan
Prodigy 110 points

Part Number: TDA4VM

Hi,

Based on my previous post and ti recommendation, I have a system up and running.

One clarification I would like is regarding pinmux config to the I/O pads in the MCU R5F/SBL/Uboot-SPL level in tiboot3.bin FW.

I have enabled couple of peripherals and the associated pinumx/pinctrl in the U-boot SPL device tree with "bootph-all" property. I expected the MCU R5F to configure the pads and apply pinctrl to the peripheral. I verifed the final device tree blob shows these nodes as "okay" and also has bootph-all tag. I disabled these on A72 Uboot + Linux and used it on a MAIN DOMAIN R5F core with FreeRTOS.

For some reason, the peripherals (MAIN UART1/FSS0_OSPI1) didn't come up and looked like under reset.

As a test, same peripherals worked fine when enabled in Linux and tested them with utils.  So the linux driver is doing something different than my FreeRTOS app which narrowed it dowm to the pins themselves.  

I had to apply the pinmux in my FreeRTOS application to bring up the peripheral and then use it.

This is different than what was recommended by TI in my earlier post.

What's going wrong in the Uboot-spl for k3-r5 ? It won't configure these peripherals even though the device tree says to do so ? What is the best way to manage this ?

I tried two versions of device tree updates and both didn't work : 

1. Only setup pinmux pads, pinctrl but disable the peripheral

2. Setup pinmux, pinctrl and enable the peripheral  

Thanks,

Prasanna

  • 0
    TI__Guru**** 171170 points

    Hi,

    Please share the patch with the changes that you have done. We will review and get back.

    - Keerthy

  • 0 in reply to Keerthy J
    Prodigy 110 points

    Hi Keerthy,

    Here is the device-tree snippet for the peripherals from my dtsi file:

    &main_uart1 {
    status = "okay";
    bootph-all;
    };

    &ospi1 {
    status = "okay";
    bootph-all;
    };

    The patch is applied to this device tree like this: 

    diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
    index c427143869c..5a767ec779e 100644
    --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
    +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
    @@ -76,3 +76,5 @@
        ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
            <0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>;
     };
    +
    +#include "my-custom-fixes.dtsi".
  • 0 in reply to Prasanna Raghunathan
    Prodigy 110 points
    Here is the snippet from the dts file generated from the u-boot.dtb file. 
    pinctrl@11c000 {
    compatible = "pinctrl-single";
    reg = <0x00 0x11c000 0x00 0x2b4>;
    #pinctrl-cells = <0x01>;
    pinctrl-single,register-width = <0x20>;
    pinctrl-single,function-mask = <0xffffffff>;
    bootph-all;

    main-uart0-default-pins {
    pinctrl-single,pins = <0x1d4 0x54001 0x1c0 0x10001 0x1e8 0x54000 0x1ec 0x10000>;
    bootph-all;
    phandle = <0x5c>;
    };

    main-uart1-default-pins {
    pinctrl-single,pins = <0x1f8 0x54000 0x1fc 0x10000>;
    bootph-all;
    phandle = <0x5d>;
    };
    mcu-fss0-ospi1-default-pins {
    pinctrl-single,pins = <0x34 0x10000 0x50 0x10000 0x40 0x54000 0x44 0x54000 0x48 0x54000 0x4c 0x54000 0x3c 0x54000 0x38 0x54000>;
    bootph-all;
    phandle = <0x16>;
    };
    serial@2810000 {
    compatible = "ti,j721e-uart\0ti,am654-uart";
    reg = <0x00 0x2810000 0x00 0x100>;
    interrupts = <0x00 0xc1 0x04>;
    clock-frequency = <0x2dc6c00>;
    power-domains = <0x08 0x116 0x01>;
    clocks = <0x09 0x116 0x00>;
    clock-names = "fclk";
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <0x5d>;
    bootph-all;
    };

    spi@47050000 {
    compatible = "ti,am654-ospi\0cdns,qspi-nor";
    reg = <0x00 0x47050000 0x00 0x100 0x00 0x58000000 0x00 0x8000000>;
    interrupts = <0x00 0x349 0x04>;
    cdns,fifo-depth = <0x100>;
    cdns,fifo-width = <0x04>;
    cdns,trigger-address = <0x00>;
    cdns,phase-detect-selector = <0x02>;
    clocks = <0x09 0x68 0x00>;
    power-domains = <0x08 0x68 0x01>;
    #address-cells = <0x01>;
    #size-cells = <0x00>;
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <0x16>;
    bootph-all;

    flash@0 { ... }
  • 0 in reply to Prasanna Raghunathan
    Prodigy 110 points

    Do I have to make the base device tree itself mark these nodes with bootph-all ?

    My custom.dtsi is getting applied too late for the SPL ?

    "fdtgrep" is stripping out these nodes even before my include is applied ?

  • 0 in reply to Prasanna Raghunathan
    TI__Mastermind 19080 points

    HI Prasanna,

    Prasanna Raghunathan said:
    have enabled couple of peripherals and the associated pinumx/pinctrl in the U-boot SPL device tree with "bootph-all" property. I expected the MCU R5F to configure the pads and apply pinctrl to the peripheral. I verifed the final device tree blob shows these nodes as "okay" and also has bootph-all tag. I disabled these on A72 Uboot + Linux and used it on a MAIN DOMAIN R5F core with FreeRTOS.
    Prasanna Raghunathan said:
    For some reason, the peripherals (MAIN UART1/FSS0_OSPI1) didn't come up and looked like under reset.
    Prasanna Raghunathan said:
    So the linux driver is doing something different than my FreeRTOS app which narrowed it dowm to the pins themselves. 

    Just to gain more clarity , this is the issue right:

    Problem Statement: R5 SPL(configure pads in device tree, but not configuring) -> peripherals are disabled in A72SPL, UBOOT and Linux-> Freertos(had to configure the pinmux, since R5 SPL is not configuring it).

    Peripherals: MAIN UART1 AND FSS0_OSPI1 are not getting enabled by R5 SPL and hence it had to be explicitly enabled in FreeRTOS.

    Objective: Wants the peripherals to be enabled in FreeRtos by R5 SPL without having to explicity apply the pinmux in the FreeRTOS application again to bring up the peripheral.

    Prasanna Raghunathan said:
    I disabled these on A72 Uboot + Linux and used it on a MAIN DOMAIN R5F core with FreeRTOS.
    • Can you share the file which you have changed as well as the changes made for disabling the peripheral on A72 UBOOT.
    • Can you also enable the peripheral on A72 UBOOT along with R5 SPL(I believe, you have enabled it)and see if the peripherals are getting configured in the FREERTOS side.

    Other Questions:

    • SDK version: Can you share the SDK version you are using and from which SDK are you taking the tiboot3.bin,tispl.bin and u-boot.img file.
    • Is there any other peripheral other than MAINUART1 and FSS0_OSPI1 which you are trying to enable, and are those peripherals and their pinmuxes getting enabled.
    • Can you also ensure that the padconfig registers you are using for the UART and OSPI pinmux are not overwritten by any other pinmux setting assigned to these padconfig registers by any other peripheral. It could be that the padconfig registers are getting overwritten by some other peripheral .Hence , just check once if these padconfig register/pinctrls used for UART/OSPI are used somewhere else in the device tree.

    Can you also share the decompiled file(dts) of the dtb present in "<u-boot folder>build/r5/spl/dts/k3-j721e-r5-common-proc-board.dtb",so that I can analyze it.

    Best Regards

    Gokul Praveen

  • 0 in reply to Gokul Praveen
    Prodigy 110 points

    Hi Gokul,

    I am not comfortable sharing the entire decompiled device tree here which is why I shared the snippets from the same.  Let me know your email address and I can send the files to you or setup a fileshare to access it. 

    Your understanding of problem statement is correct. I am interested only in these two peripherals. The objective is also correct. I want to maintain all pinmux configs centralized to the R5-SPL and not scatter it across which was also the TI recommended way.

    I have already verified that these pins are not used for any other purpose. To avoid the override issue, I am including my custom device tree file right at the end of the k3-j721e-r5-common-proc-board.dts file. So any previous settings should automatically get override by my custom fix.

    Here is the version info: TI-ARAGO SDK version : 2025.01 PDK Version : 11_02_00_06

    Thanks,

    Prasanna

  • 0 in reply to Prasanna Raghunathan
    TI__Mastermind 19080 points

    Hi Prasanna.

    Prasanna Raghunathan said:
    I am not comfortable sharing the entire decompiled device tree here which is why I shared the snippets from the same.  Let me know your email address and I can send the files to you or setup a fileshare to access it. 

    No Problem, Prasanna. Can you share the code snippet of MAIN UART1 and OSPI1 nodes in the  decompiled file(dts) of the dtb present in "<u-boot folder>/build/r5/spl/dts/k3-j721e-r5-common-proc-board.dtb", as you the uboot.dtb file snipper shared earlier is not the desired file.

    Prasanna Raghunathan said:
    For some reason, the peripherals (MAIN UART1/FSS0_OSPI1) didn't come up and looked like under reset.
    Prasanna Raghunathan said:
    disabled these on A72 Uboot + Linux and used it on a MAIN DOMAIN R5F core with FreeRTOS.

    I believe, that A72 SPL/A72 UBOOT/LINUX is still configuring it.

    Can you try these 2 alternatives:

    • Alternative 1:Entirely, remove the MAIN UART1 and OSPI1 nodes from the A72 SPL,A72UBOOT and Linux device tree.
    • Alternative 2: Instead of status="disabled" , try replacing it with status="reserved" in A72 SPL, A72 UBOOT and Linux.

    Best Regards

    Gokul Praveen