AM2432: Could AM2432 Support Two Individual Ethercat Master

Part Number: AM2432
Other Parts Discussed in Thread: AM2434

Hi TI Experts,

Customer has a new SST project that needs to run 3 Ethercat loops to control 3 phases separately. On each of the slave side of the corresponding phase, custoemer used F28P65 to run 100M ethercat slave. Previously customer plans to use 3*AM26 (since AM26 feedback each AM26 only supports single Ethercat master stack) running Ethercat master IBV stack to connect with the F28P65 respectively.

Now to reduce the BOM cost, customer planned to use single AM24 to run two independant IBV ethercat master loops (replacing 2 * AM26, the rest of the third AM26 will not change) and connect to two F28P65 (this will take 4 ethernet ports, since each ethercat loop takes 2 ethernet ports: 1 for Rx, 1 for Tx).

The Ethercat master stack vendor is IBV, only needs to run 100M Ethercat master, and the cycle time for each ethercat loop is 100us, now the question is:

  • Does AM2432 support to run two individual IBV ethercat master loops on AM2432?
  • Will run two ethercat master loops individually affect the ethercat performance? (e.g. any risk of achieving the 100us cycle time)
  • Will run two IBV ethercat master require customer choosing the ALV package of AM24 to support DDR? (AM26 expert feedback one IBV ethercat master is sufficient without DDR)

Thanks,

Kevin

  • Hi Kevin,

    Does AM2432 support to run two individual IBV ethercat master loops on AM2432?

    in theory that should work, provided that they're using two ICSSGs or an ICSSG and a CPSW port. What won't work is using two ports of the same ICSSG. Please note that we haven't tested such a setup yet.

    Will run two ethercat master loops individually affect the ethercat performance? (e.g. any risk of achieving the 100us cycle time)

    For performance on AM24x the most critical part is fast memory. The 64KB of TCM per core and 2MB MSRAM in total should be sufficient for two instances, but you might have to optimize by disabling unused features. Apart from that I don't expect that the two instances could negatively effect each other's performance.

    Do you know if they're planning to use only 2 R5f cores, or is there a chance that they need the other 2 cores for application usage? If they use only 2 cores, that could double the TCM to 128 KB per R5f.

    Will run two IBV ethercat master require customer choosing the ALV package of AM24 to support DDR? (AM26 expert feedback one IBV ethercat master is sufficient without DDR)

    Same answer as above, with the caveat that they really have to make everything fit into TCM+MSRAM, and can't optimize by moving non-critical parts to DDR memory.

    Are you able to share more about their required feature set? E.g. using the configuration library on the target requires way more memory than the master itself. There are other features enabled by default like EoE, FoE and SoE that might not be relevant for their use-case, that could further allow to reduce the memory footprint.

    Best Regards,

    Dominic

  • Hi Dominic,

    Thanks for the feedback, it is helpful.

    I think at least it is clear that we are supposed to achieve the two ecat master in parallel without DDR on AM24 if we have done enough optimizations as you suggested above.

    As for 128KB TCM topic, if customer only used 2 R5f cores, normally they will select AM2432 (1 cluster dual core versions with 1 TCM), so in this case each ECAT ring still uses 64KB TCM, the 128KB TCM is true only when customer select/pay for AM2434 (2 cluster 4 core versions with 2 TCM) but only use 2 R5f cores. Anyway this is an option to consider, but we will firstly try using 2*64KB TCM + 2MB RAM to handle two ECAT master.

    For the required feature set, since customer is new to apply ECAT in SST, so they do not have the exact feature set for now, we are still in the promotion stage for introducing AM24+AM26 handling 3 ECAT master based on IBV to let customer buy in our solution, customer will have a better understanding on this after they reached to IBV for ECAT master details.

    Thanks,

    Kevin

  • Hello Kevin,

    are you sure about AM2432 being a single cluster with 1 TCM only? The datasheet says "2x Single Core R5F0_0 R5F1_0". I was always under the assumption that the AM2432 would have two clusters, and I'm pretty sure I've read that on E2E somewhere, too.

    Regards,

    Dominic

  • Hi Dominic,

    Sorry, you are correct, yes i have double checked that AM2432 enabled 2*R5f cores locating from two cluster separately, so each of the R5f core could use the 128KB TCM.

    Thanks,

    Kevin

  • What won't work is using two ports of the same ICSSG.

    Does the EtherCAT ring need the two port from different ICSSG?

    The use case is two ECAT master, each is a ring.

  • Ah, so they need a ring for cable redundancy? Can you comment on what other features they need? Does the use-case require distributed clocks and/or hot-connect? Can you estimate how many subdevices there will be on one ring, and how much process data each subdevice requires?

    For CR you can use two ports of the same ICSSG. The two master instances need to use separate ICSSGs.

  • Hi Dominic,

    I have visited customer today. Please see the details below:

    1: Since SST is highly safety oriented, AM24 needs to run 2 Ethercat Ring in parallel, each master processing in separate ICSSG unit.

    2: There are 10 subdevices in each Ethercat Ring, each subdevice process ~60 bytes data. Each Ethercat Ring is 100M speed with 100us cycle time.

    3: Distributed Clock is must required in each Ethercat Ring, customer told me they recently have reached to your team about this, but seems currently distributed clock is not supported in Ethercat Ring, customer hopes you could start implementing this feature soon.

    4: Hot-connect is not required if item 3 is supported.

    Thanks,

    Kevin