AIC3106 on EVM omap L137/c6747

tharangini chinnadurai

Hi,

I am using the example code audio_edma_c6747.prj (the talkthrough code using AIC3106 and C6747). The example program has been configured for 48KHz sampling rate. When I change this to 8KHz, it still operates (transmits and receives) in 48KHz. I have changed the mcasp.c part of the example code from this (48KHz):

EVMC6747_AIC3106_rset( AIC3106_PAGESELECT, 0 ); // Select page 0
EVMC6747_AIC3106_rset( AIC3106_RESET, 0x80 ); // Reset AIC3106

    EVMC6747_AIC3106_rset( 3, 0x22 ); // 5 PLL A                            <- [PLL=OFF][Q=4][P=2]
    EVMC6747_AIC3106_rset( 4, 0x20 ); // 4 PLL B                            <- [J=8]
    EVMC6747_AIC3106_rset( 5, 0x6E ); // 5 PLL C                            <- [D=7075]
    EVMC6747_AIC3106_rset( 6, 0x23 ); // 6 PLL D                            <- [D=7075]

    EVMC6747_AIC3106_rset( 7, 0x0A ); //0x6A);//0x0A ); // 7 Codec Datapath Setup             <- [FS=48 kHz][LeftDAC=LEFT][RightDAC=RIGHT]
    EVMC6747_AIC3106_rset( 8, 0x00 ); // 8 Audio Interface Control A       <- [BCLK=Slave][MCLK=Slave]
    EVMC6747_AIC3106_rset( 9, 0x00 ); // 9 Audio Interface Control B       <- [I2S mode][16 bit]
    EVMC6747_AIC3106_rset( 10, 0x00); // 10 Audio Interface Control C       <- [Data offset=0]
    EVMC6747_AIC3106_rset( 15, 0 );    // 15 Left ADC PGA Gain              <- [Mute=OFF]
    EVMC6747_AIC3106_rset( 16, 0 );    // 16 Right ADC PGA Gain              <- [Mute=OFF]
    EVMC6747_AIC3106_rset( 19, 0x04 ); // 19 LINE1L to Left ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
    EVMC6747_AIC3106_rset( 22, 0x04 ); // 22 LINE1R to Right ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
    EVMC6747_AIC3106_rset( 27, 0 );    // 27 Left AGC B                     <- [OFF]
    EVMC6747_AIC3106_rset( 30, 0 );    // 30 Right AGC B                     <- [OFF]
    EVMC6747_AIC3106_rset( 37, 0xE0 ); // 37 DAC Power & Output Dvr          <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]
    EVMC6747_AIC3106_rset( 38, 0x10 ); // 38 High Power Output Dvr           <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
    EVMC6747_AIC3106_rset( 43, 0 );    // 43 Left DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
    EVMC6747_AIC3106_rset( 44, 0 );    // 44 Right DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
    EVMC6747_AIC3106_rset( 47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume         <- [Routed]
    EVMC6747_AIC3106_rset( 51, 0x09 ); // 51           HPLOUT Output         <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset( 58, 0 );    // 58           HPLCOM Output         <- []
    EVMC6747_AIC3106_rset( 64, 0x80 ); // 64 DAC_R1 to HPROUT Volume         <- [Routed]
    EVMC6747_AIC3106_rset( 65, 0x09 ); // 65           HPROUT Output         <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset( 72, 0 );    // 72           HPRCOM Output         <- []
    EVMC6747_AIC3106_rset( 82, 0x80 ); // 82 DAC_L1 to LEFT_LOP/M Volume     <- [Routed]
    EVMC6747_AIC3106_rset( 86, 0x09 ); // 83 LINE2R to LEFT_LOP/M Volume     <- []
    EVMC6747_AIC3106_rset( 92, 0x80 ); // 92 DAC_R1 to RIGHT_LOP/M Volume    <- [Routed]
    EVMC6747_AIC3106_rset( 93, 0x09 ); // 93           RIGHT_LOP/M Output    <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset( 101, 0x01 ); // 101 GPIO Control Register B        <- [CODEC_CLKIN = CLKDIV_OUT]
    EVMC6747_AIC3106_rset( 102, 0 );    // 102 Clock Generation Control       <- [PLLCLK_IN and CLKDIV_IN use MCLK]

to this:(8KHz)

    EVMC6747_AIC3106_rset( AIC3106_PAGESELECT, 0 );       // Select page 0
    EVMC6747_AIC3106_rset( AIC3106_RESET, 0x80 );         // Reset AIC3106
   EVMC6747_AIC3106_rset( 2, 0xAA );
    EVMC6747_AIC3106_rset( 3, 0x92 ); // 5 PLL A                            <- [PLL=OFF][Q=4][P=2]
    EVMC6747_AIC3106_rset( 4, 0x04)// 4 PLL B                            <- [J=1]
    EVMC6747_AIC3106_rset( 5, 0x46) // 5 PLL C                            <- [D=4512
    EVMC6747_AIC3106_rset( 6, 0x20) // 6 PLL D                            <- [D=4512]

Please send me an example code that uses AIC3106 (you could just modify the audio_edma_c6747.prj) has been configured for 8KHz.

Thanks

over 13 years ago

0 tharangini chinnadurai over 13 years ago

Intellectual 980 points

I have attached the project herewith for your reference. It is only the audio_edma_c6747 example with changes in only 4 lines in mcasp.c (the place where 8KHz sampling rate is configured instead of 48KHz sampling rate)0537.audio_edma_c6747.zip

0 tharangini chinnadurai over 13 years ago in reply to tharangini chinnadurai

Intellectual 980 points

Hi,

some more information:

I measure the output (transmitting from the codec to the outside world via headphone) frequency using the following method:

I fill the ping buffer fully with 0x7FFFFFFF and pong buffer fully with 0x0 and I use oscilloscope (CRO) and measiure the output square wave in the headphone jack out (connector). The period of one full square wave (positive side +negative side) is 3.3msec for 80 samples. Thus, I infer that sampling rate is 48KHz. No matter what values I use in registers 2 to 6 (that is EVMC6747_AIC3106_rset( 2, to 6)) I get only 3.3ms per period (the ping and pong buffers are 40 words long each- that is 80 samples per transmission)

Please let me know how to configure the AIC3106 to operate at 8KHz sampling rate for the EVM OMAP L 137 c6747 board

0 Joe Coombs over 13 years ago in reply to tharangini chinnadurai

TI__Expert 8890 points

Tharangini,

In this application, the AIC3106 is not driving the McASP clocks (i.e. BCLK and MCLK, which correspond to ACLKX or AHCLKX respectively). The BCLK signal is the one that you want to operate at 32 x 8 kHz; that signal is being generated by the McASP peripheral. To reduce your sampling rate, you will need to adjust the clock division in the McASP peripheral using the ACLKXCTL register.

On the EVM, we use an externally generated 24.576 MHz clock signal to drive AHCLKX and MCLK. Inside the McASP peripheral, you can divide this down by between 1 and 32 to obtain the ACLKX signal. Unfortunately, the lowest sampling rate you can achieve with this setup is 24 kHz (i.e. 24.576 MHz / 32 bits per sample / 32 = 24 kHz. To get down to 8 kHz, you may need to try changing the source for AHCLKX from the external pin to the internal AUXCLK signal, to which you can apply additional division (in the AHCLKXCTL register). Alternatively, you could create your own board with a slower external audio clock.

Hope this helps.

0 tharangini chinnadurai over 13 years ago in reply to Joe Coombs

Intellectual 980 points

Hi Joe,

Thank you for your reply. I tried changing the external audio clock from 24.576MHz to 2.048MHz. I have set the registers such that the WCLK is 8KHz and the ADC and DAC sampling rate of the codec(AIC3106) are 8KHz. But now, I get white noise+the desired audio signal output in the audio_edma_c6747 example. Also the output audio (which has white noise) is not clear.When I increase the ADC and DAC sampling rate of the codec from 8KHz to 32KHz, I get a more clear audio output(but still it has white noise). Also I observed that the quality of the output audio(but there is still white noise even for 32KHz-quality has improved in the sense, I can clearly hear the words in the audio output when using ADC and DAC sampling rate =32KHz, but I cannot hear the words clearly when using ADC and DAC sampling rate=8KHz. But there is some white noise in all the combinations) increases as I increase the ADC and DAC sampling rate from 8KHz to 16KHz, 24KHz, 32KHz.

Any ideas to get rid of the white noise and get a clear audio output at ADC and DAC sampling rate=8KHz?

Thanks.

0 tharangini chinnadurai over 13 years ago in reply to tharangini chinnadurai

Intellectual 980 points

Hi Joe,

More Information: I changed the external clock to 2.048MHz by replacing the clock generator chip from 24.576MHz to another 2.048MHz chip

0 tharangini chinnadurai over 13 years ago in reply to tharangini chinnadurai

Intellectual 980 points

// Configure AIC3106 registers
    EVMC6747_AIC3106_rset( 2, 0xAA );
    EVMC6747_AIC3106_rset( 3, 0x22 ); // 5 PLL A                            <- [PLL=OFF][Q=4][P=2]
    EVMC6747_AIC3106_rset( 4, 0x20 ); // 4 PLL B                            <- [J=8]
    EVMC6747_AIC3106_rset( 5, 0x6E ); // 5 PLL C                            <- [D=7075]
    EVMC6747_AIC3106_rset( 6, 0x23 ); // 6 PLL D                            <- [D=7075]
    EVMC6747_AIC3106_rset( 7, 0x0A ); // 7 Codec Datapath Setup             <- [FS=48 kHz][LeftDAC=LEFT][RightDAC=RIGHT]
    EVMC6747_AIC3106_rset( 8, 0x00 ); // 8 Audio Interface Control A       <- [BCLK=Slave][MCLK=Slave]
    EVMC6747_AIC3106_rset( 9, 0x00 ); // 9 Audio Interface Control B       <- [I2S mode][16 bit]
    EVMC6747_AIC3106_rset( 10, 0x00); // 10 Audio Interface Control C       <- [Data offset=0]
    EVMC6747_AIC3106_rset( 15, 0 );    // 15 Left ADC PGA Gain              <- [Mute=OFF]
    EVMC6747_AIC3106_rset( 16, 0 );    // 16 Right ADC PGA Gain              <- [Mute=OFF]
    EVMC6747_AIC3106_rset( 19, 0x04 ); // 19 LINE1L to Left ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
    EVMC6747_AIC3106_rset( 22, 0x04 ); // 22 LINE1R to Right ADC            <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS]
    EVMC6747_AIC3106_rset( 27, 0 );    // 27 Left AGC B                     <- [OFF]
    EVMC6747_AIC3106_rset( 30, 0 );    // 30 Right AGC B                     <- [OFF]
    EVMC6747_AIC3106_rset( 37, 0xE0 ); // 37 DAC Power & Output Dvr          <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd]
    EVMC6747_AIC3106_rset( 38, 0x10 ); // 38 High Power Output Dvr           <- [HPRCOM=SingleEnd][ShortCircuit=OFF]
    EVMC6747_AIC3106_rset( 43, 0 );    // 43 Left DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
    EVMC6747_AIC3106_rset( 44, 0 );    // 44 Right DAC Digital Volume        <- [Mute=OFF][Gain=0dB]
    EVMC6747_AIC3106_rset( 47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume         <- [Routed]
    EVMC6747_AIC3106_rset( 51, 0x09 ); // 51           HPLOUT Output         <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset( 58, 0 );    // 58           HPLCOM Output         <- []
    EVMC6747_AIC3106_rset( 64, 0x80 ); // 64 DAC_R1 to HPROUT Volume         <- [Routed]
    EVMC6747_AIC3106_rset( 65, 0x09 ); // 65           HPROUT Output         <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset( 72, 0 );    // 72           HPRCOM Output         <- []
    EVMC6747_AIC3106_rset( 82, 0x80 ); // 82 DAC_L1 to LEFT_LOP/M Volume     <- [Routed]
    EVMC6747_AIC3106_rset( 86, 0x09 ); // 83 LINE2R to LEFT_LOP/M Volume     <- []
    EVMC6747_AIC3106_rset( 92, 0x80 ); // 92 DAC_R1 to RIGHT_LOP/M Volume    <- [Routed]
    EVMC6747_AIC3106_rset( 93, 0x09 ); // 93           RIGHT_LOP/M Output    <- [Mute=OFF][Power=ON]
    EVMC6747_AIC3106_rset( 101, 0x01 ); // 101 GPIO Control Register B        <- [CODEC_CLKIN = CLKDIV_OUT]
    EVMC6747_AIC3106_rset( 102, 0 );    // 102 Clock Generation Control       <- [PLLCLK_IN and CLKDIV_IN use MCLK]

    // Initialize MCASP1
    mcasp = &MCASP_MODULE_1;

    /* ---------------------------------------------------------------- *
     *                                                                  *
     * McASP1 is in MASTER mode.                                       *
     *      BCLK & WCLK come from McASP1                                *
     *      DIN is used by write16/write32                              *
     *      DOUT is usec by read16/read32                               *
     *                                                                  *
     * ---------------------------------------------------------------- */

    mcasp->regs->GBLCTL = 0;       // Reset
    mcasp->regs->RGBLCTL = 0;       // Reset RX
    mcasp->regs->XGBLCTL = 0;       // Reset TX
    mcasp->regs->PWRDEMU = 1;       // Free-running

    // RX
    mcasp->regs->RMASK      = 0xffffffff; // No padding used
    mcasp->regs->RFMT       = 0x00018078; // MSB 16bit, 1-delay, no pad, CFGBus
    mcasp->regs->AFSRCTL    = 0x00000112; // 2TDM, 1bit Rising, INTERNAL FS, word
    mcasp->regs->ACLKRCTL   = 0x000000A7; // Rising INTERNAL CLK,(from tx side)
    mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (from tx side)
    mcasp->regs->RTDM       = 0x00000003; // Slots 0,1
    mcasp->regs->RINTCTL    = 0x00000000; // Not used
    mcasp->regs->RCLKCHK    = 0x00FF0008; // 255-MAX 0-MIN, div-by-256

    // TX
    mcasp->regs->XMASK      = 0xffffffff; // No padding used
    mcasp->regs->XFMT       = 0x00018078; // MSB 16bit, 1-delay, no pad, CFGBus
    mcasp->regs->AFSXCTL    = 0x00000112; // 2TDM, 1bit Rising edge INTERNAL FS, word
    mcasp->regs->ACLKXCTL   = 0x000000A7; // ASYNC, Rising INTERNAL CLK, div-by-16
    mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK
    mcasp->regs->XTDM       = 0x00000003; // Slots 0,1
    mcasp->regs->XINTCTL    = 0x00000000; // Not used
    mcasp->regs->XCLKCHK    = 0x00FF0008; // 255-MAX 0-MIN, div-by-256

    mcasp->regs->SRCTL5     = 0x000D;     // MCASP1.AXR1[5] --> DIN
    mcasp->regs->SRCTL0     = 0x000E;     // MCASP1.AXR1[0] <-- DOUT
    mcasp->regs->PFUNC      = 0;          // All MCASPs
    mcasp->regs->PDIR       = 0x14000020; // All inputs except AXR0[5], ACLKX1, AFSX1

    mcasp->regs->DITCTL     = 0x00000000; // Not used
    mcasp->regs->DLBCTL     = 0x00000000; // Not used
    mcasp->regs->AMUTE      = 0x00000000; // Not used

    // Starting sections of the McASP
    mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON;                                    // HS Clk
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
    mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON;                                    // HS Clk
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );

    mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON;                                     // Clk
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );
    mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON;                                     // Clk
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );

    mcasp->regs->XSTAT = 0x0000ffff;        // Clear all
    mcasp->regs->RSTAT = 0x0000ffff;        // Clear all

    mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON;                                      // Serialize
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );
    mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON;                                      // Serialize
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );

    // Write a 0, so that no underrun occurs after releasing the state machine
    mcasp->regs->XBUF5 = 0;
    mcasp->regs->RBUF0 = 0;

    mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON;                                       // State Machine
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
    mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON;                                       // State Machine
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );

    mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON;                                        // Frame Sync
    while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
    mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON;                                        // Frame Sync
    while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );
}

0 tharangini chinnadurai over 13 years ago in reply to tharangini chinnadurai

Intellectual 980 points

The white noise went away after I used the following values:

    // Configure AIC3106 registers
    EVMC6747_AIC3106_rset( 2, 0xAA );//Fsref/6=8KHz
    EVMC6747_AIC3106_rset( 3, 0x11); // 5 PLL A                            <- [PLL=OFF][Q=2][P=1]
    EVMC6747_AIC3106_rset( 4, 0xC0); // 4 PLL B                            <- [J=48]
    EVMC6747_AIC3106_rset( 5, 0x0); // 5 PLL C                            <- [D=0]
    EVMC6747_AIC3106_rset( 6, 0x0); // 6 PLL D                            <- [D=0]

The above means, I have configured WCLK of McASP = 2.048MHz, so MCLK of codec = 2.048KHz, P=1, K=48,J=48,D=0,R=1.Using these values Fsref=48KHz. The only problem is Q. I dont enable Q. So, I have to configure the correct value for Q. Q=CLKDIV_IN/(Fsref*128) = 2048000/(48000 * 128)=0.3333, unfortunately Q can neither be set to 0 nor to 0.333, not even 1.

What should be the value of Q?

But the audio output still sounds like coming from a deep well!

0 Joe Coombs over 13 years ago in reply to tharangini chinnadurai

TI__Expert 8890 points

Tharangini,

You may want to consider using the AIC3106's internal PLL to generate the sample clock. This should give you finer control to reach the sample rate that you want using the P, R, J, and D values. I believe that the Q value is not used by the PLL. For more information, please refer to the "AUDIO CLOCK GENERATION" section of the AIC3106 datasheet.

For in-depth questions about the AIC3106 or other audio codecs, I recommend posting on the audio converters forum. I'll do my best to support you here, but we are reaching the limits of my expertise with this device. :)

0 vincent stefanus over 12 years ago in reply to Joe Coombs

Prodigy 140 points

Hi joe, please I need your help
actually I want to set the sampling rate to 48 KHz, can you tell me how to configure the AHCLKX of MCASP so I get my sampling rate to 48 KHZ
can you tell me how to make the configure the clock division ?
thanks

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AIC3106 on EVM omap L137/c6747