[FAQ] AM62A7: DCC, SDL Clock Configuration

The Dual Clock Comparator (DCC) is a hardware diagnostic module used to determine the accuracy of a clock signal during application runtime. It measures the frequency of a selectable Test Clock (CLK1) source using a known, reliable Reference Clock (CLK0) source.

The DCC can also be configured to operate in single-shot or continuous mode. In single-shot mode, DCC performs a one-time countdown where DCC stops operation when the counters reach 0. A completion interrupt is raised and the status can be checked. In continuous mode, DCC reloads both counts with the seed value upon completion without error. In case of an error, an ESM error event is raised.

DCC Input Source Clock Mapping:

DCC Instance- Multiple instances exist on a single SoC so that several clocks can be monitored simultaneously and independently.

• There are 6 Main domain DCC Instances: DCC0 - DCC6 and 2 MCU domain DCC Instances: MCU_DCC0 / MCU_DCC1

Each DCC Instance has two independent counter paths:

• Counter 0 (CLK0) - typically driven by a known reference.
• Counter 1 (CLK1) - typically driven by the clock under test.

Each DCC instance exposes two clock source selection registers:

• DCCCLKSRC0  →  selects which clock feeds Counter 0 (Can take value: 0-3)
• DCCCLKSRC1  →  selects which clock feeds Counter 1 (Can take value 0-9)

Example: DCC0 Input Source Clock Mapping

• The Input/Mux defines the counter path → If 0 value will be written in DCCCLKSRC0 register and If 1 value will be written in DCCCLKSRC1 register.
• The DCCCLKSRC0/DCCCLKSRC1 value determines the clock source which has to be mapped.

The DCC Input Clock Source Mapping can be found in AM62Ax Sitara Processors Technical Reference Manual.

AM62Ax Sitara Processors Technical Reference Manual (Rev. C)

4.15.1.3 DCC Input Source Clock Mapping (AM62A):

Source Clock Frequency:

Open the Clock Tree tool within SysConfig to visually trace a component to its clock source and read the operational frequency.

• Software Product: AM6X Clock Tree (1.1.4)
• Device: AM62A3-Q1

Source Clock Frequency:

Open the Clock Tree tool within SysConfig to visually trace a component to its clock source and read the operational frequency.

• Software Product: AM6X Clock Tree (1.1.4)
• Device: AM62A3-Q1

Start the design →  Search the component of interest

Example: C7X256V0_C7XV_CORE_0

The clock source for C7X256V0_C7XV_CORE_0 is PLL7_hsdiv0 and the frequency reaching C7X256V0_C7XV_CORE_0 is 850 MHz.

→ To find the DCC mapping of the above source clock source i.e PLL7_hsdiv0 refer to the The DCC Input Clock Source Mapping table in AM62Ax Sitara Processors Technical Reference Manual.

The C7X256V0_CLK (or PLL7_hsdiv0 ) clock source is mapped to DCC3 instance → DCC_CLKSRC2_CLK.

DCC Counter Operation

CLK0 (reference) ──→ [ Counter 0 ] ──→ counts down from SEED0 ---→ when counter reaches 0, VALID_SEED0 count down starts

CLK1 (test clock) ──→ [ Counter 1 ] ──→ counts down from SEED1 ---→ Counter1 should reach 0 during the time when VALID0 is running, else ESM error is raised      

Clock Source Configuration

→ How To Configure Clock Source:

SDL_DCC_Config configParams;

configParams.mode = SDL_DCC_MODE_CONTINUOUS;   /*DCC Configured in Continuous Mode */

configParams.clk0Src = SDL_DCC_CLK0_SRC_CLOCK0_2; /* Select Input0 to be CLOCK0[2] */
configParams.clk1Src = SDL_DCC_CLK1_SRC_CLOCKSRC2;  /* Select Input1 to be CLKSRC2 */

→ To Calculate The Seed Values: 

Below functions are defined in the MCU+SDK DCC Example to calculate the Seed Values,

• SDL_DCCAppGetClkRatio(clk0Freq, clk1Freq, &refClkRatioNum, &testClkRatioNum); 
• SDL_DCCAppSetSeedVals(clk0Freq, clk1Freq, refClkRatioNum, testClkRatioNum, APP_DCC_TEST_CLOCK_SRC_1_DRIFT, &configParams);   /* APP_DCC_TEST_CLOCK_SRC_1_DRIFT → Allowed drift in percentage (+/-) */

For detailed DCC compute calculations, refer to Continuous Monitor of the PLL Frequency With the DCC App Note.

The SDL DCC seed values calculation is based on DCC Computation Tool for AM263x MCU

→ Configure MCU DCC Instance 0 seed values and clocks:

SDL_DCC_configure(SDL_DCC_INST_MCU_DCC0, &configParams); 

→ Enable Error Interrupt for MCU_DCC0:

SDL_DCC_enableIntr(SDL_DCC_INST_MCU_DCC0, SDL_DCC_INTERRUPT_ERR);

→ For Single-Shot Mode, Enable Done Interrupt:

SDL_DCC_enableIntr(SDL_DCC_INST_MCU_DCC0, SDL_DCC_INTERRUPT_DONE);

→ Enable DCC Instance:

SDL_DCC_enable(SDL_DCC_INST_MCU_DCC0);