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SRIO_SGMII Clock inputs

Hector Rivera
Intellectual 2025 points

Hi,

I have a customer asking the follwowing question.

I have a question about the SRIO_SGMII Clock inputs.  We’re planning to use the SGMII Ethernet interface on the 6671, and we wanted to use a differential 125MHz clock as the input.  However, sections 3.3 and 7.4.1 of the Hardware Design Guide state that only clocks between 156MHz and 312MHz can be used.  I was hoping to get some more information as to why the minimum input frequency is set at 156MHz, especially if we only decide to use the Ethernet at 10/100 speeds.

 

Regards,

Hector Rivera

  • 0
    TI__Intellectual 1880 points

    Hector,

    This requirement is due to the SGMII SerDes PLL. The minimum input frequency supported by the PLL is 156.25 MHz.

  • 0 in reply to Derek Brown
    TI__Mastermind 30825 points

    Hector,

    Another comment here.  The SGMII operates at 1.25GHz period (1Gbaud after 8b/10b.) Even when the link rate is 10 or 100mbps, the data is transmitted at 1gbaud speed over SGMII, it's just repeated 10x for 100mbps and 100x for 10mbps link rates.

    Best Regards,
    Chad

  • 0 in reply to Derek Brown
    TI__Mastermind 42545 points

    Hector,

    While the SGMII SERDES PLL has the flexibility to be programmed to use a 125MHz reference clock, the C6671 was not characterized at that clock frequency.  Mulitpling a lower reference clock frequency results in greater jitter so as the reference frequency is decreased the clock is required to have less jitter to compensate.  We standardized on three reference clock frequencies, 156.25MHz, 250MHz and 312.5MHz, and characterized the part using them and this allowed us to provide clear jitter templates for these frequencies.  Consequently these are the only three frequencies that we can support as reference frequencies across temperature and voltage.  This is true no matter what frequency is used at the PHY interface to the network.  The SGMII interface will run at the same frequency regardless of the speed the PHY has negotiated with the network.  For 100Mbit or 10Mbit network connections the SGMII will simply repeat the data either ten times or one hundred time depending on the negotiated speed.  Since the SGMII is operating at the same speed the jitter requirements for the reference clock don't change.