Part Number: TDA4VEN-Q1
Hello,
Regarding the TDA4VEN I have the following questions:
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USB3SS (USB1) Subsystem: For the TDA4VEN-Q1 USB3SS (USB1) subsystem, does Device/Peripheral mode support SuperSpeed (5 Gbps), or is Device mode limited to High Speed (480 Mbps)? The USB3SS capability list in the TRM appears to show SuperSpeed under Host only.
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Decoupling Caps: Where can decoupling cap recommendations for TDA4VEN power be found?
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OLDI (unused feature): If OLDI is not being used, what is the recommended pin connection for its power pin VDDA1P8_OLDI0? Should it be left unconnected?
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SERDES Block – REFCLK for PCIe only: Is the external SERDES REFCLK (REFCLK_P/N) required ONLY for PCIe? For a design with no PCIe, can these pins be left unused?
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SERDES Block – SGMII clocking: Can the SERDES CORE_REF_CLK be sourced from the internal MAIN_PLL2_HSDIV0 for SGMII, and does the internal reference meet SGMII jitter requirements without an external REFCLK?
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SERDES Block – USB3 clocking: Can the SERDES run USB3 from an internal reference, or does USB3 SuperSpeed require an external low-jitter REFCLK? If external is required, what frequency/jitter spec applies?
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SERDES Block – PCIe clock output: Can the SoC (as PCIe Root Port) source a PCIe clock output on SERDES REFCLK (REFCLK_P/N) for the endpoint device while meeting PCIe jitter spec?
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SERDES Block – Unused REFCLK termination: If REFCLK_P/N is left unused (internal clocking used instead), how should these pins be terminated?
Any and all help on the matter would be greatly appreciated.