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TDA4VE-Q1: Debugger support

Poongodi Rangasamy
Prodigy 10 points

Part Number: TDA4VE-Q1
Other Parts Discussed in Thread: J721EXCPXEVM, DRA829, TDA4VM

I'm a new user to TI processors. I'm using J721EXCPXEVM common board together with J721S2XSOMG01EVM for TDA4VE processor.
Currnelty we're using the internal XDS110 for debugging with CCS.
We've plans to buy XDS560v2 for better debugging, while checking we've come across the availability of Lauterbach Trace32 debugger support also for this processor.
Is it possible to debug,
- multicore i.e, A72 and R5F cores(for IPC communication / hypervisor working)
- multiple break points
- time b/w two breakpoints
Can you suggest, which one to use,
- Internal XDS110
- Or which one to get XDS560v2 system trace or Laturbach Trace32 debugger without power trace.

  • 0
    TI__Mastermind 26185 points

    Hello,

    Sorry for the delayed reply as I was out.

    Several 3rd party debuggers support the J721E (TDA4VM, DRA829) SOC. Which one to use will depend on what you are familiar with and which layer of software you need to develop/debug on.  For full concurrent debug of multi-core with a hypervisor probably Lauterbach is the preferred option as it will support concurrent debug for your host, guest, and hypervisor thanks to mmu and rtos/hlos awareness features (see www.lauterbach.com/.../tda4vm for bundling options).  If your hypervisor is one from a vendor like GHS, their native tools might be a better choice.  A CCS/XDS debugger will work one address space at a time and is commonly used for RTOS based targets.

    Regards,
    Richard W.
  • 0
    Prodigy 10 points

    Thank you for your reply. You said that with CCS/XDS debugger we can work one address space at a time.

    Is it meant that with CCS and XDS560v2 System trace, can't i debug the A72 core for IPC communication? Because in the manuals i'm seeing, i can debug multicore debugging also using CCS/XDS. Kindly state the limitations of multicore debugging using the debugger XDS560v2, i'm planning to use this for IPC communication.

  • 0 in reply to Poongodi Rangasamy
    TI__Mastermind 26185 points

    You mention wanting a hypervisor. This implies your A72 will be running at least 2 operating systems and a hypervisor.  This would amount to 'at least' 3 address spaces, actually more as Linux will have one per process.  CCS can debug 1 at a time on the A72 as it will only know the 1 address space given by 1 .out file. You can try to manually control for this it but you will need to do a lot of work. TRACE32 can debug all of them concurrently as it uses the VMID + it can track per-process spaces, it does this by fully understanding the MMU usage for stage1 and stage2 users.  It allows loading of multiple .out files each with its own qualified address space id. 

    Yes, if you want to debug between two cores each with their own address space you can use CCS or other debuggers.  You attach to each core with a different debugger instance.  The debugger can cross coordinate if run groups are setup or CTI linkages.   If you want to debug IPC between to freertos R5's which use a single .out per core that will work well enough.