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Ethernet problem on custom board

Vladimir Karakozov
Expert 2285 points

Hi, all!

I have custom board based on DM816x EVM. On my board is placed PHY Ethernet chip KSZ8051MNL (instead  LSI ET1011C on EVM).

Can I use DaVinci EMAC driver from davinci_emac.c source code. I replaced EMAC_MDIO_PHY_MASK to 0xFFFFFFFF and after that my PHY device was detected as GENERIC, and no more. Values of registers from PHY device and CPU MDIO is correct (to my mind). Board connected to local network. If I try use ping or dhcp command I have no any result. Please tell me, which parts of the DaVinci EMAC driver I need to change? I can provide any additional information - schematic, software code, and so on. Thank you.

Power up board
MMC:   OMAP SD/MMC: 0
Net:   board_eth_init()
Detected MACID:40:5f:c2:27:d:50
davinci_emac.c: davinci_emac_initialize()
davinci_emac.c: davinci_eth_mdio_enable()
davinci_emac.c: davinci_eth_phy_detect()
davinci_eth_phy_detect(), ALIVE = 0x00000080
davinci_emac.c: davinci_eth_mdio_info() - VERSION = 0x40070106
davinci_emac.c: davinci_eth_mdio_info() - CONTROL = 0x4104007c
davinci_emac.c: davinci_eth_mdio_info() - ALIVE = 0x80
davinci_emac.c: davinci_eth_mdio_info() - LINK = 0x80
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_mdio_info() - PHY_BMCR = 0x3500
davinci_emac.c: davinci_eth_mdio_info() - PHY_BMSR = 0x786d
davinci_emac.c: davinci_eth_mdio_info() - PHY_PHYIDR1 = 0x22
davinci_emac.c: davinci_eth_mdio_info() - PHY_PHYIDR2 = 0x1555
davinci_emac.c: davinci_eth_mdio_info() - PHY_ANAR = 0x1e1
davinci_emac.c: davinci_eth_mdio_info() - PHY_ANLPAR = 0x45e1
davinci_emac.c: davinci_eth_mdio_info() - PHY_ANER = 0x7
davinci_emac.c: davinci_eth_mdio_info() - PHY_ANNPTR = 0x2001
davinci_emac.c: davinci_eth_mdio_info() - PHY_ANLPNP = 0x0
davinci_emac.c: davinci_eth_mdio_info() - Extended registers
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_mdio_info() - 0x17 = 0xfe30
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_mdio_info() - 0x1B = 0x29
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_mdio_info() - 0x1D = 0x0
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
Ethernet PHY: GENERIC @ 0x07
miiphyutil.c: miiphy_register()
miiphy_register: added 'GENERIC @ 0x07', read=0xc070c01c, write=0xc070bf5c
DaVinci EMAC
Hit any key to stop autoboot:  0
Environment variables:
ethaddr=40:5f:c2:27:0d:50
ethact=DaVinci EMAC
ipaddr=192.168.0.99
netmask=255.255.255.0
Ping
#ping 192.168.0.39
davinci_emac.c: davinci_eth_close()
davinci_emac.c: davinci_eth_ch_teardown(1)
davinci_emac.c: davinci_eth_ch_teardown(0)
davinci_emac.c: davinci_eth_open()
davinci_emac.c: davinci_eth_mdio_enable()
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_write(0x7)
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_write(0x7)
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_write(0x7)
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: gen_get_link_speed(0x7) - Link is Up
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: davinci_eth_open() - set EMAC for Full Duplex
davinci_emac.c: davinci_eth_open() - MACCONTROL = 0x21
Using DaVinci EMAC device
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: gen_get_link_speed(0x7) - Link is Up
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: gen_get_link_speed(0x7) - Link is Up
davinci_emac.c: davinci_eth_send_packet() - send 60 bytes
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: gen_get_link_speed(0x7) - Link is Up
davinci_emac.c: davinci_eth_phy_read(0x7) - Ok
davinci_emac.c: gen_get_link_speed(0x7) - Link is Up
davinci_emac.c: davinci_eth_send_packet() - send 60 bytes
davinci_emac.c: davinci_eth_close()
davinci_emac.c: davinci_eth_ch_teardown(1)
davinci_emac.c: davinci_eth_ch_teardown(0)
ping failed; host 192.168.0.39 is not alive



								


				
				

				
			

		

			
						
									
                			    			                        
						
						
			
			
						
			                        
			
			
				
			  
			

			     
			

		


				    			

						
















	

	

					
    
	
    





		
	
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                          Intellectual
                        855 points
                      
    
                          
                   		
		
    
					
    Hi idle,
    

    what's the autonegotiated speed? Does KSZ8051MNL support fix for the TX_CLK EMAC issue?
    

    -Robert
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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						in reply to Robert F.
					
									
    
	
    
	                                    
                      
    
                        
                          Expert
                        2285 points
                      
    
                          
                   		
		
    
					
    Hi, Robert F! 
    

    Thank you for your attention!
    

    > What's the autonegotiated speed?
    

    There I can control value of speed? Board connected to 100Mbps local network switch (on switch, when I connect the cable, the LED is on). After power up board, KSZ8051MNL Basic Status register value PHY_BMSR = 0x786d. Bit description (from data sheet): 
    

    bit14 = 1 - Capable 100 Mbps full duplex
    

    bit13 = 1 - Capable 100 Mbps half duplex
    

    bit12 = 1 - Capable 10 Mbps full duplex
    

    bit11 = 1 - Capable 10 Mbps half duplex
    

    bit6 = 1 - Preamble suppression
    

    bit5 = 1 - Auto-negotiation process complete
    

    bit4 = 0 - No remote fault 
    

    bit3 = 1 - Capable to perform auto-negotiation
    

    bit2 = 1 - Link is up
    

    bit0 = 1 - Supports extended capabilities registers
    

    > Does KSZ8051MNL support fix for the TX_CLK EMAC issue? 
    

    Can you explain more details about this problem? This is hardware issue?
    

    I saw Clock ~2MHz on pin12 KSZ8051MNL.
    

    I don't saw anything on pin23 (TXEN) while ping or dhcp.
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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						in reply to Vladimir Karakozov
					
									
    
	
    
	                                    
                      
    
                        
                          Intellectual
                        855 points
                      
    
                          
                   		
		
    
					
    I only know there is errata about 1Gb - but looks like KSZ8051 is 10/100Mb only
    

    http://www.ti.com/litv/pdf/sprz328c
    

    Advisory 1.1.18 CPGMAC 1-Gbps Mode Does Not Work When EMAC_TXCLK is Not Running
    Revisions Affected: 1.1, 1.0
    


    Details: Although EMAC_TXCLK is specific to the 10/100Mbps clock, if it is not running, then the
    1-Gbps mode does not work.
    


    In Ethernet boot, when the board is powered on, the Ethernet PHY chip auto-negotiates
    and establishes a link at either 10/100/1000 Mbps speed. If the link is established at 1
    Gbps, the Ethernet boot does not work for PHY chips that do not provide the
    EMAC_TXCLK clock signal. According to the GMII specification, the EMAC_TXCLK
    signal is not required to be provided by the PHY for 1-Gbps mode of operation, hence
    some of the PHYs may not provide this clock. In these cases, the Ethernet boot fails.
    Workaround: Use the PHY chip that outputs the transmit clock to MAC (EMAC_TXCLK pin) (e.g.,
    ET1011C PHY).
    Ensure that the PHY does not auto-negotiate to 1 Gbps by default, until boot occurs. At
    a later stage, the second-level bootloader or OS driver can enable 1-Gbps mode in the
    PHY via MDIO and restart auto-negotiation to switch to gigabit mode. A PHY chip might
    provide an input pin to disable/enable 1-Gbps mode by default, which can be overridden
    by using MDIO register settings.
    

    

    Check silicon revision and errata of your PHY. I had once an issue with Micrel PHY as they changed pinout between different silicons.
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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                          Expert
                        2285 points
                      
    
                          
                   		
		
    
					
    Ok. I will check all parameters. 
    

    Board booting from NAND (or SPI) and then I need ethernet to load Linux kernel and mount NFS.
    

    Do you have any suggestions? Can you look at the schematic list, may be there is some error?I can't attach any file or image :(
    

    

    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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						in reply to Vladimir Karakozov
					
									
    
	
    
	                                    
                      
    
                        
                          Intellectual
                        855 points
                      
    
                          
                   		
		
    
					
    I had very similar issue - Micrel PHY connected ok, but ETH didn't work. The problem was, as I mentioned before, pin difference between silicon revisions - they swapped TX_CLK and RESET. This may not be your case - I only mentioned it, because I had this problem with Micrel PHY and symptoms were similar.
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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                          Expert
                        2285 points
                      
    
                          
                   		
		
    
					
    Please explain to me how a EMAC subsytem determines which lines from EMAC_TXD[0-7] and EMAC_RXD[0-7] are connected?
    

    On my board I have connected only EMAC_TXD[0-3] and EMAC_RXD[0-3], but on EVM all of them are connected. In u-boot code and in DaVinci EMAC driver I can't found that I need to change in my case?
    

    Thank you.
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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						in reply to Vladimir Karakozov
					
									
    
	
    
	                                    
                      
    
                        
                          Expert
                        2285 points
                      
    
                          
                   		
		
    
					
    It was schematic problem on custom board. After reset CONFIG[0-2] was set in illegal mode. I rewrite PHY-bootstrap settings, and now I have Ethernet on my board!!! I will try to boot linux kernel :) Thank's for all.
    
			
    

		
		
		
		
	
    
	
    
		
    
			
		
    
	
    

	            
                	
	
    
				
		                
                
                
                
                
                
                
        		
		
				
    
			
		
    
		
		 
		
		
     
    
	
    

    
			
    
			
    
		
    

		
    
	
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