DRA821U-Q1: [Escalation Request] J7200 SDK 11.2 - Kernel Panic on Resume from SOC OFF (E2E #1661286)

Part Number: DRA821U-Q1

Hi TI Jacinto Support Team,

This is Jack Cha, FAE Technical Manager at Arrow Electronics.

I am reaching out to request your urgent attention and support regarding an unresolved E2E thread (ID: 1661286). Our customer is currently experiencing a critical blocker on the J7200 EVM using the latest Processor SDK Linux 11.2.

• E2E Link: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1661286/...

To summarize, a kernel panic (Asynchronous SError in ti_cpsw_proxy_client) consistently occurs about 15 seconds after resuming from the SOC OFF state. This is 100% reproducible on the standard EVM, regardless of the triggering process. It appears to be related to the CPSW power/clock initialization sequence during the wakeup phase.

As this issue is completely blocking the customer's power management development and system stability tests, could you please provide an update on the following?

1. Has the TI factory team successfully reproduced this issue, and what is the current debugging status?

2. Is there any temporary workaround or manual interface control method we can suggest to the customer to unblock their testing while waiting for an official patch?

We would highly appreciate it if you could escalate this ticket to the relevant engineering team for a prompt resolution.

Thank you for your strong support as always.

Best regards,

Jack Cha
FAE Technical Manager
Arrow Electronics