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C5515 DMA with I2S1

Todd Anderson78572
Guru 14640 points

All:

The C5515 is set up in Mono DSP slave I2S, 24-bit word width.

We are using the DMA to send multiple I2S words to a companion chip. So far, when the I2S transaction happens, the first of 10 words is sent out. The second word is not sent, even though the DMA is set up for increment source buffer. The first word is sent 10 times, and never gets beyond that.

All of the examples shown in the DMA User's Guide show peripheral-to-memory, but in this case we have a situation of memory-to-peripheral. Has anyone done this, and are there setup particulars that we need to be aware of?

Regards,

Todd Anderson

 

  • 0
    Prodigy 80 points

    Hi Todd,

    have you connected the I2S EVENT to trigger next DMA action? Something like this:

    /* Setup DMA1 for I2S2 */

        DMA_Config dmaConfig;

        dmaConfig.pingPongMode = DMA_PING_PONG_ENABLE;

        dmaConfig.autoMode     = DMA_AUTORELOAD_ENABLE;

        dmaConfig.burstLen     = DMA_TXBURST_1WORD;

        dmaConfig.trigger      = DMA_EVENT_TRIGGER;

        dmaConfig.dmaEvt       = DMA_EVT_I2S2_TX;

        dmaConfig.dmaInt       = DMA_INTERRUPT_ENABLE;

        dmaConfig.chanDir      = DMA_WRITE;

        dmaConfig.trfType      = DMA_TRANSFER_IO_MEMORY;

        dmaConfig.dataLen      = ENCODED_DMA_BUF_LEN*4;

        dmaConfig.srcAddr      = (uint32_t)i2s2DmaOutputLeftBuffer;

        dmaConfig.destAddr     = (uint32_t) & (hI2s2->hwRegs->I2STXLT0);

        dma1LeftTxHandle = DMA_open(DMA_CHAN4, &dma1LeftTxObj, &status);

        status = DMA_config(dma1LeftTxHandle, &dmaConfig);

    assert(STATUS_OK == status);

  • 0 in reply to henrik gilvad
    Prodigy 80 points

    Also check that srcAddr points to the memory block you want transmitted and that destAddr points to the I2STXLT0 or I2STXRT0.
    There might be an addressing issue. Some needs Byte-addressing, other places you need Word-addressing.

  • 0 in reply to henrik gilvad
    Guru 14640 points

    Thanks for getting back to me...

    I am using DMA3 on I2S1 Left, so some of my settings are going to be different. I have a similar setup, but here are the differences:

    PingPong mode is disabled.

    AutoReload is disabled - should that be enabled?

    Dma event setup is CSL_DMA_EVT_I2S1_TX

    dataLen is set to 4. You have "encoded dma buf length x 4." That might be a key - I did not have any success with a value other than 4 in this field.

    Can you elaborate on how you up the dataLen variable. I will try some of these changes to see if it will have an effect on my DMA setup.

    Regards,

    Todd Anderson

     

    ;

     

  • 0 in reply to Todd Anderson78572
    Prodigy 80 points

    If you don't want to reprogram the src register then you have to set AutoReload to enabled.

    DMA3 on I2S1 is correct.

    I have used both 4, 8, 16 and 32 in length but you must program the dma.dataLen to Bytelength * 4.

    Br

    Henrik

     

  • 0 in reply to Todd Anderson78572
    Guru 14640 points

    The key was changing the Length. I now have a string of 10 32-bit values being sent out per DMA cycle.

    Regards,

    Todd Anderson

  • 0 in reply to Todd Anderson78572
    Guru 14640 points

    All:

    There is an interrupt associated with DMA activity, and in order to make this a "recurring" interrupt, I found that the following two instructions were placed inside the interrupt service routine:

    ifrValue = CSL_SYSCTRL_REGS->DMAIFR;

    CSL_SYSCTRL_REGSS->DMAIFR = ifrValue;

    When I include the above code into the ISR, I Do get recurring interrupts, but I am not sure why. Can someone explain why this works?

    Regards,

    Todd Anderson

  • 0 in reply to Todd Anderson78572
    Prodigy 80 points

    Hi Todd,

     

    Reading the Interrupt Flag Register remembers which interrupt-sources have triggered.
    Writing the bits in the CSL_SYSCTRL_REGS->DMAIFR clears the given interrupt(s) so they can occur again.

    So it's a handshake mechanism to tell that now we have serviced the interrupt and are ready for the next.

    Br
    Henrik Gilvad