Problem with MDIO link status register on C6678 EVM board

Jochen,

The RJ45 connector has an ACT LED and a LINK LED.  Is the LINK LED on solid or does is flicker?  Are there any registers that indicate the robustness of the link?

Have you performed a read test on the PHY?  Most of the registers contain a static value.  If you read them repeatedly, do you always get the correct value?

The PHY is a Marvell part.  If you have proven the MDC/MDIO link is robust and the DSP driver is robust, you will need to get support directly from Marvell.  Our NDA with them does not allow us to distribute datasheets.

Tom

Thanks Tom,

the link LED is on solid.

I did a read test on PHY register 2 and 3 (they should be statically), and no, i don't get always correct values. Here's a sample of register 2: (it ends when the first time the ACK bit in the USERACCESS register wasn't set after a read request)

[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x283
[C66xx_0] PHY reg 2 data 0xf2db
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x143
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141

thanks for any help,

jochen

Jochen,

Have you slowed down the interface to determine whether this is a contributing factor?

Tom

I tried some (maybe 3 different) mdio clock settings between 1MHz (divider of 165) and 2.5MHz (divider of 67) without any effect. is a setting slower than 1MHz worth a try?

Jochen,

Yes, take it down under 100 KHz and see if that makes a difference.

Tom

No difference. tried around 80KHz (divider 2000).

the only notable thing is that always the same numbers appear.

283 looks a bit like a shift left, 143 like a toggling bit. So indeed a clock problem isn't a bad guess i assume.

[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x283
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x283
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x143
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x143
[C66xx_0] PHY reg 2 data 0x283
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0x283
[C66xx_0] PHY reg 2 data 0x143
[C66xx_0] PHY reg 2 data 0x141
[C66xx_0] PHY reg 2 data 0xf2db
[C66xx_0] PHY reg 2 data 0x141

Jochen,

Can you read back the registers written by CSL to make sure they are getting modified properly?  Similarly, can you measure the clock with a scope to verify the expected clock rate?

Tom

Good morning Tom,

Readback of the registers is reliable and the correct values.

The MDIO clock signal MDC looked good. Clear signal with the expected 2.5V on PHY side. Measured frequency was 63kHz. the MDIO clock divider was setup as 2000. So i would have expected a clock of 83kHz. (CPU running on 1GHz, SYSCLK7 (i hope that one is the one MDC is derived from) is set to 1/6).

jochen

Jochen,

Can you please measure the frequency at the SYSCLKOUT pin (pin AE3). You can use test point 12 (TP12) on the EVM to measure this signal. This is the same DSP/6 clock that is used for MDIO input clock, and should be 166.67 MHz for 1 GHz CPU operation.

Before measuring this pin, please make sure that the SYSCLKOUTEN field (bit 0) in the DEVCFG register (address 0x0262014C) is set to 1.

Hi Derek,

the SYSCLKOUT pin shows exact 166MHz.

Regards, Jochen

Jochen,

SYSCLKOUT is the expected 166MHz indicating the core clock is properly programmed for 1000MHz.  Since your divider is programmed to 2000, you should get 83KHz on the MDC clock pin.  Can you recheck this value and plug in other values and measure the frequency?  This should be deterministic.

Tom

Hi,

rechecked MDC frequency:

divider 2000: 62.0kHz

divider 1000: 125.0kHz

divider 500: 250.0kHz

i know that 166MHZ divided by 1000 isn't 125kHz, but the scope is sure that the MDC runs at those speeds.

regards,

jochen

Jochen,

I am still working on this issue, and just wanted to give you an update. I have done some testing where I changed the frequency of the system clock, and after making this change, I did not see any change in the frequency of the MDC. I also tried updating the frequency of the PA clock and the SGMII clock, and also did not observe the MDIO clock change. 

I am currently trying to determine which clock is being used to generate the MDC, but based on the testing that I have done so far, it looks like the MDC is not derived from the system clock, the PA clock, or the SGMII clock.

I will send out another update as soon as I have more information.

Thanks for the update.

Please let me know if i can help somehow.

jochen

Any news in the meantime?

Regards,

Jochen

Jochen,

You have good timing. I was able to confirm that the input frequency that is used to generate the MDC is 125 MHz, so you are seeing the correct frequency on your board. I was also able to determine that the input clock is generated by the SGMII SerDes module, so you need to make sure that the SerDes is setup before trying to setup the MDIO and establish a link with PHY.

Also, could you please send me the SerDes settings that you are using? 

Hi,

Thanks for the update.

I am using

platform_init()

of \pdk_C6678_1_0_0_17\packages\ti\platform\evmc6678l\platform_lib\src\platform.c, which calls

configSerdes()

and

Init_SGMII(1)

of \pdk_C6678_1_0_0_17\packages\ti\platform\evmc6678l\platform_lib\src\evmc6678_phy.c

Regards,

jochen

Jochen,

I took a quick look at the SerDes settings and they should be okay. I will need to do some experimentation. I will get back with you soon.

Jochen,

Is your code enabling the EXT_EN bit in the MAC Control register? I found this post where someone was having trouble with the link when the EXT_EN bit was set, and the issue went away when the EXT_EN bit was cleared.

Good morning Derek,

yes, the EXT_EN bit was enabled in my code. But unfortunately clearing it didn't have any effect. Still failing.

jochen

Hello.

I have the same MDIO behaviour on TMDSEVM6678LE Rev. 2A.  Sometimes PHY 88E1111 incorrectly answers to DSP request - see attached bad.png (C1, C2 -  DSP side, C3, C4 - PHY side). Is seems PCA9306DCUT is not a good choice for the level shift. 

 Is there a solution to make the MDIO on TMDSEVM6678LE  to work properly?

Kostantin,

This does not appear to be a level translation problem.  This appears to be contention where both the DSP and PHY are driving the bit at the same time.  Can you try slowing the MDC and seeing whether this helps?

Tom