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PCIe PM on DM814x

Itamar Ben Zaken
Prodigy 40 points


I am trying to bring up a PCIe EP with the DaVinci platform (TMDXEVM8148). However, I am a bit confused regarding the RC support of L1.

On one hand, the DM81xx user guide says it supports L1, but on the other hand:

root@dm814x-evm:# ./lspci -vvv
00:00.0 Class 0604: Device 104c:8888 (rev 01)
        ...
        ...
        Capabilities: [40] Power Management version 3
                Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
                Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
        ...


Does the RC on TMDXEVM8148 support L1 and PME?

  • 0
    TI__Expert 5685 points

    The default is D1, D2 disabled. The s/w currently doesn't handle PM (both device and link states).

    Of course, ASPM with L1 transition can be enabled (which too is disabled by default).

       Hemant

  • 0 in reply to HemantPedanekar
    TI__Prodigy 40 points

    Thanks.

    But we've also encountered some problems with ASPM:

    1. The LinkCap register in the RC says the RC does not support ASPM L1:

    00:00.0 Class 0604: Device 104c:8888 (rev 01)
            ...
            Capabilities: [70] Express (v2) Root Port (Slot-), MSI 00
                    ...
                    LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s, Latency L0 <2us, L1 <64us


    2. We cannot seem to perform a read while RC is in L0s - after enabling ASPM in the RC, a read fails:

    # setpci -v -s 01:00.0 0x80.B=0x3
    0000:01:00.0 @80 03
    # setpci -v -s 01:00.0 0x80.B
    0000:01:00.0 @80 = ff

  • 0 in reply to Itamar Ben Zaken
    TI__Expert 5685 points

    Hello,

    1. LInk capability register bits for ASPM need to be set to enable L1, it is disabled by default.

    2. Do you want to do setpci -v -s 00:00.0 instead of setpci -v -s 01:00.0?

    Irrespective of this, I think the registers should still be accessible (you can check using devmem2 on PCIe local and remote config registers) but since driver doesn't support/understand ASPM, it allows config access only in L0 and returns 0xffffffff otherwise.

        Hemant

  • 0 in reply to HemantPedanekar
    TI__Prodigy 40 points

    [1] Will try that ASAP.

    [2] It wasn't a mistake - I was trying to enable L0s ASPM in *both* the RC and EP.

    Also, devmem2 seemed to be able to access the EP.

    Thanks for the help.

    Itamar B

  • 0 in reply to Itamar Ben Zaken
    TI__Expert 5685 points

    Itamar Ben Zaken said:

    Also, devmem2 seemed to be able to access the EP.

    Yes, that will work as it is the RC driver which rejects access to PCI/e config when not in L0 as I mentioned.

       Hemant

  • 0 in reply to HemantPedanekar
    TI__Prodigy 40 points

    Now we are witnessing an odd behavior..

    1. I ensure the RC and EP both have L0s and L1 ASPM in their Link Capability registers
    2. I enable L0s and L1 ASPM on both the RC and EP
    3. EP sends ASPM L1 REQ upstream
    4. RC sends PM REQ ACK downstream
    5. EP sends EIOS and the upstream link is now down
    6. both idle for 196ns
    7. RC continues to send PM REQ ACK downstream
    8. both idle for 64ns
    9. RC sends TS1
    10. upstream link is now up

    Can you help me understand [7] and [9] - why doesn't the RC send EIOS?

    Thanks.
    Itamar B