AM6422: eMMC Part Reuse (SDINBDG4-8G-XI1) on AM422 - Reference Design Compliance & Design Considerations

Hello Daniel,

Thank you for your query !

Daniel Cheng1 said:

1. Is it necessary to strictly follow the AM422 reference design (EVM) for this eMMC, or are alternative routing/power configurations acceptable?

A1. Please consider the AM64x EVM (i.e. the latest TMDS64EVM or SK-AM64B) eMMC hardware interface implementation as a TI eMMC recommended solution. Though the EVM hardware have passed through many tests and were proven to be sustainable solutions over time, a hardware interface design for production purposes and specific environments/ applications may impose additional requirements.

I have some questions regarding customer design:

Q1.1. What is meant under different power configuration than AM64x EVM one - does this mean any change in the eMMC power-up / power-down or other power supplies trigger changes ? 

Q1.2. How noisy is the environment in which the product shall operate ?

Q1.3. Are there any EMI restrictions for the designed product ?

Q1.4. Are there any concerns on the PCB layout sizing ? 

Q1.5 What is the highest speed eMMC mode (supported by both AM64x eMMC Host and the memory) that the customer's bootloader / application shall use ?

Depending on the mode, the MMC0 - eMMC Host Controller allowed ranges of: input slew rate and output load capacitance shall be considered. Respecting these Datasheet MMC0 - eMMC constraints will guarantee an eMMC nominal timing behavior. Please refer the below Table, MMC0 Timing Conditions of the AM64x Datasheet / Chapter, Specifications / Section, Timing and Switching Characteristics / Section, Peripherals/ Section, MMCSD / Section, MMC0 - eMMC Interface 

For the eMMC PCB routing you shall consider as a reference the same table on:

• allowed propagation delay per each of the eMMC signal pcb trace
• the maximum allowed difference in propagation delay between all high speed eMMC signals - data, command, clock and data strobe.

Please consider also the following quite informative Sitara FAQ on recommended eMMC hardware i/f design practices. Some of the sections discussing the AM64x / AM243x - specific eMMC hardware i/f implementation:

FAQs on recommended eMMC hardware i/f design practices

Daniel Cheng1 said:

Are there any specific hardware, software (Linux/RTOS drivers), timing constraints, or boot device compatibility issues we should pay attention to?

A2: If customer needs the AM64x ROM to boot any customer SBL / SPL from the SDINBDG4-8G-XI1 memory, the memory supported modes shall be compatible to the ROM supported eMMC boot modes. Also, the SDINBDG4-8G-XI1 eMMC Memory hardware reset input is recommended to be connected to a AM64x RESETSTATz output driven logic, which means that eMMC hardware reset function shall be enabled in the ext_CSD register (if not enabled by default). For more information regarding ROM eMMC boot options, refer the subsections of the  AM64x TRM/ Chapter Initialization / Section, eMMC Boot.

Q2.1 Which eMMC memory supported mode ( SDR/ DDR & freq.) is considered for booting ? 

Regarding software constraints, can you please let us know which Linux SDK and MCU-PLUS SDK (RTOS) versions customer is considering to use ?

Looking forward to your feedback !

Best Regards,

Anastas Yordanov