AM6548: AM6548 MCU_BOOTMODE POST Selection Clarification

Part Number: AM6548

Hello,

I would like to clarify the interpretation of the POST selection defined by MCU_BOOTMODE[8:5] in AM65x TRM Table 4-4.

Our intention is to enable the following POST tests at power-on: DMSC LBIST, MCU LBIST, MCU PBIST

Could you please clarify the following?

1. Does MCU_BOOTMODE[5] = 1 by itself enable both DMSC LBIST and MCU LBIST, or does it only select parallel execution of LBISTs that must additionally be enabled through bits 6 and 7?
2. For enabling MCU PBIST + DMSC LBIST + MCU LBIST in parallel, is the recommended MCU_BOOTMODE[8:5] setting 1001 or 1111?
3. If 1111 is used, what is the behavior of bits 6 and 7 while bit 5 is also set? Are the individual LBIST selections ignored/merged with the parallel selection, or could the tests be executed separately in addition to the parallel execution?
4. If MCU_BOOTMODE[8:5] = 1110 is used instead, PBIST, DMSC LBIST and MCU LBIST are selected individually while the parallel LBIST selection is disabled. How does the POST execution differ between 1110 and 1001? In particular, are DMSC LBIST and MCU LBIST executed sequentially with 1110 and in parallel with 1001?
5. Is there a measurable or specified difference in POST/boot execution time between 1110 and 1001? If so, could you provide the expected execution times or the recommended configuration where startup time is important?
6. Is the diagnostic coverage identical between the 1110 and 1001 configurations, assuming both configurations execute DMSC LBIST, MCU LBIST and MCU PBIST successfully?

This clarification is important for us because the POST configuration is part of our functional-safety startup diagnostics, and we would like to select the configuration that provides the required diagnostic coverage without redundant test execution or unnecessary startup delay.

Thank you in advance.

Kind regards,
Hamdi Ertan YASAR